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DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating with JESD204A interface
Rev. 01 -- 26 May 2009 Objective data sheet
1. General description
The DAC1408D650 is a high-speed 14-bit dual channel Digital-to-Analog Converter (DAC) with selectable 2x or 4x interpolating filters optimized for multi-carriers WCDMA transmitters. Thanks to its digital on-chip modulation, the DAC1408D650 allows the complex I and Q inputs to be converted up from baseband to IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register. The DAC1408D650 also includes a 2x and 4x clock multiplier which provides the appropriate internal clocks and an internal regulation to adjust the output full scale current. The input data format is serial according to JESD204A specification. This new interface has numerous advantages over the traditional parallel one: easy PCB layout, lower radiated noise, lower pin count, self-synchronous link, skew compensation. DAC1408D650 maximum number of lanes is 4 and its maximum serial data rate is 3.25 Gbps.
2. Features
I Dual 14-bit resolution I 650 Msps maximum update rate I SFDR: -75 dBc; fs = 640 Msps; fo = 4 MHz I IMD3: 74 dBc; fs = 640 Msps; fo = 154 MHz I Inverse (sin x) / x function I Embedded complex modulator
I Four JESD204A serial input lanes I Differential CML receiver with termination I LMF = 421 or LMF = 211 support I 3 or 4 wire SPI configuration interface I Input data rate up to 325 Msps or I Differential scalable output current from 162.5 Msps 1.6 mA to 22 mA I Selectable 2x or 4x interpolation filters I External analog offset control (10-bit auxiliary DACs) I Two's complement or Binary Offset I Internal digital offset control Data Format (BODF) I Very low noise cap free integrated PLL I On-chip 1.25 V reference
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating I Industrial temperature range from -40 C to +85 C I Typical power dissipation: 1.19 W I Power down and Sleep modes
I 32-bit programmable NCO frequency I Low power NCO option I LVDS compatible clock inputs
3. Applications
I I I I I I I Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA Communication: LMDS/MMDS, point to point Direct Digital Synthesis (DDS) Broadband wireless systems Digital radio links Instrumentation Automated Test Equipment (ATE)
4. Ordering information
Table 1. Ordering information Package Name DAC1408D650HW/C1 HTQFP100 Description plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad Version SOT638-1 Type number
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
2 of 88
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5. Block diagram
SDO SDIO SCS_N SCLK
INTER LANE ALIGNMENT
VIN_P1 VIN_N1
LANE PROC
FRAME ASSEMBLY
Objective data sheet Rev. 01 -- 26 May 2009 3 of 88
DAC1408D650_1 (c) NXP B.V. 2009. All rights reserved.
NXP Semiconductors
SPI CONTROL REGISTERS
NCO 32 bits frequency setting 16 bits phase adjustment cos sin
10 BITS OFFSET CONTROL
AUX. DAC
AUXAP AUXAN
SYNC_OUTP SYNC_OUTN
DIGITAL LAYER PROCESSING FIR 1 FIR 2 X Sin X
10 BITS GAIN CONTROL IOUTAP + I DAC IOUTAN
VIN_P0 VIN_N0
LANE PROC
x2
x2
DAC1408D
VIN_P2 VIN_N2
SINGLE SIDE BAND MODULATOR
OFFSET CONTROL
REF. BANDGAP AND BIASING
VIRES GAPOUT
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
LANE PROC
FIR 1
FIR 2 X Sin X + Q DAC IOUTBN 10 BITS GAIN CONTROL IOUTBP
VIN_P3 VIN_N3
LANE PROC
x2
x2
PLL CLKINP CLKINN CLOCK GENERATOR UNIT
DAC1408D650
10 BITS OFFSET CONTROL
AUX. DAC
AUXBP AUXBN
CLKP
CLKN
RESET_N
001aak160
Fig 1.
Block diagram
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
6. Pinning information
6.1 Pinning
99 VDDA(1V8) 97 VDDA(1V8) 95 VDDA(1V8) 93 VDDA(1V8) 83 VDDA(1V8) 81 VDDA(1V8) 79 VDDA(1V8) 77 VDDA(1V8) 91 IOUTAN 85 IOUTBN
90 IOUTAP
86 IOUTBP
98 AGND
92 AGND
80 AGND
100 AGND
78 AGND
89 AGND
87 AGND
84 AGND
82 AGND
96 AGND
94 AGND
VDDA(3V3) AUXAP AUXAN AGND VDDA(1V8) VDDA(PLL)(1V8) AGNDPLL CLKP CLKN
1 2 3 4 5 6 7 8 9
76 AGND
88 n.c.
75 VDDA(3V3) 74 AUXBP 73 AUXBN 72 AGND 71 VDDA(1V8) 70 VDDA(1V8) 69 GAPOUT 68 VIRES 67 n.c. 66 RESET_N 65 SCS_N 64 SCLK
DGNDPLL 10 VDDD(PLL)(1V8) 11 n.c. 12 n.c. 13 VDD(IO)(1V8) 14 GNDIO 15 n.c. 16 n.c. 17 VDDD(1V8) 18 DGND 19 n.c. 20 n.c. 21 n.c. 22 n.c. 23 n.c. 24 n.c. 25 AGND
DAC1408D650
63 SDIO 62 SDO 61 GNDIO 60 VDD(IO)(1V8) 59 n.c. 58 n.c. 57 n.c. 56 n.c. 55 DGND 54 VDDD(1V8) 53 n.c. 52 n.c. 51 n.c.
AGNDSINTF 26
CLKINN 27
CLKINP 28
VDDA(SINTF)(1V8) 29
SYNC_OUTN 30
SYNC_OUTP 31
AGNDSINTF 32
VIN_N0 33
VIN_P0 34
VDDA(SINTF)(1V8) 35
VIN_P1 36
VIN_N1 37
AGNDSINTF 38
VIN_N2 39
VIN_P2 40
VDDA(SINTF)(1V8) 41
VIN_P3 42
VIN_N3 43
AGNDSINTF 44
TRST 45
TMS 46
TCK 47
TDI 48
TDO 49
n.c. 50
001aak167
Fig 2.
Pin configuration
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
4 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
6.2 Pin description
Table 2. Symbol VDDA(3V3) AUXAP AUXAN AGND VDDA(1V8) VDDA(PLL)(1V8) AGNDPLL CLKP CLKN DGNDPLL VDDD(PLL)(1V8) n.c. n.c. VDD(IO)(1V8) GNDIO n.c. n.c. VDDD(1V8) DGND n.c. n.c. n.c. n.c. n.c. n.c. AGNDSINTF CLKINN CLKINP VDDA(SINTF)(1V8) SYNC_OUTN SYNC_OUTP AGNDSINTF VIN_N0 VIN_P0 VDDA(SINTF)(1V8) VIN_P1 VIN_N1 AGNDSINTF VIN_N2
DAC1408D650_1
Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Type[1] P O O G P P G I I G P P G P G G I I P O O G I I P I I G I Description analog supply voltage 3.3 V auxiliary DAC B output current complementary auxiliary DAC B output current analog ground analog supply voltage 1.8 V PLL analog supply voltage 1.8 V PLL analog ground clock input complementary clock input PLL digital ground PLL digital supply voltage 1.8 V not connected not connected input/output buffers supply voltage 1.8 V input/output buffers ground not connected not connected digital supply voltage 1.8 V digital ground not connected not connected not connected not connected not connected not connected serial interface analog ground serial interface frame complementary clock input serial interface frame clock input serial interface analog supply voltage 1.8 V sync request to transmitter, complementary output sync request to transmitter serial interface analog ground serial interface lane 0 negative input serial interface lane 0 positive input serial interface analog supply voltage 1.8 V serial interface lane 1 positive input serial interface lane 1 negative input serial interface analog ground serial interface lane 2 negative input
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
5 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Pin description ...continued Pin 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Type[1] I P I I G I I I I O P G P G O I/O I I I I/O O P P G O O P G P G P G Description serial interface lane 2 positive input serial interface analog supply voltage 1.8 V serial interface lane 3 positive input serial interface lane 3 negative input serial interface analog ground JTAG Test Reset. Must be tied to GND. JTAG Test Mode Select JTAG Test Clock JTAG Test Data In JTAG Test Data Out not connected not connected not connected not connected digital supply voltage 1.8 V digital ground not connected not connected not connected not connected input/output buffers supply voltage 1.8 V input/output buffers ground SPI data output SPI data input/output SPI clock SPI chip select (active LOW) general reset (active LOW) not connected DAC biasing resistor bandgap input/output voltage analog supply voltage 1.8 V analog supply voltage 1.8 V analog ground auxiliary DAC B output complementary auxiliary DAC B output analog supply voltage 3.3 V analog ground analog supply voltage 1.8 V analog ground analog supply voltage 1.8 V analog ground
(c) NXP B.V. 2009. All rights reserved.
Table 2. Symbol VIN_P2
VDDA(SINTF)(1V8) VIN_P3 VIN_N3 AGNDSINTF TRST TMS TCK TDI TDO n.c. n.c. n.c. n.c. VDDD(1V8) DGND n.c. n.c. n.c. n.c. VDD(IO)(1V8) GNDIO SDO SDIO SCLK SCS_N RESET_N n.c. VIRES GAPOUT VDDA(1V8) VDDA(1V8) AGND AUXBN AUXBP VDDA(3V3) AGND VDDA(1V8) AGND VDDA(1V8) AGND
DAC1408D650_1
Objective data sheet
Rev. 01 -- 26 May 2009
6 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Pin description ...continued Pin 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 H[2] Type[1] P G P G O O G G O O G P G P G P G P G G Description analog supply voltage 1.8 V analog ground analog supply voltage 1.8 V analog ground complementary DAC B output current DAC B output current analog ground not connected analog ground DAC A output current complementary DAC A output current analog ground analog supply voltage 1.8 V analog ground analog supply voltage 1.8 V analog ground analog supply voltage 1.8 V analog ground analog supply voltage 1.8 V analog ground analog ground
Table 2. Symbol VDDA(1V8) AGND VDDA(1V8) AGND IOUTBN IOUTBP AGND n.c. AGND IOUTAP IOUTAN AGND VDDA(1V8) AGND VDDA(1V8) AGND VDDA(1V8) AGND VDDA(1V8) AGND AGND
[1] [2]
P: power supply; G: ground; I: input; O: output. H = heatsink (exposed die pad to be soldered)
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
7 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
7. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD(IO) VDDA(3V3) VDDA(1V8) VDDD VDDA(PLL) VDDD(PLL) VDD(sintf) Tstg Tamb Tj
[1] [2]
Parameter input/output supply voltage analog supply voltage (3.3 V) analog supply voltage (1.8 V) digital supply voltage PLL analog supply voltage PLL digital supply voltage serial interface supply voltage storage temperature ambient temperature junction temperature
Conditions
[1] [1] [2] [2] [2] [2]
Min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -55 -40 -40
Max +2.5 +4.6 +2.5 +2.5 +2.5 +2.5 +2.5 +150 +85 125
Unit V V V V V V C C C
JESD204A compliant
The supply voltage VDDA(3V3) may have any value between -0.5 V and +4.6 V provided that the supply voltage differences VCC are respected. The supply voltages VDDA(1V8), VDDD, VDDA(PLL), VDDD(PLL), VDD(IO) and VDD(sintf) may have any value between -0.5 V and +2.5 V provided that the supply voltage differences VCC are respected.
8. Thermal characteristics
Table 4. Symbol Rth(j-a) Rth(j-c)
[1]
Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions
[1] [1]
Typ 19.8 7.7
Unit K/W K/W
In compliance with JEDEC test board, in free air.
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
8 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
9. Characteristics
Table 5. Characteristics VDDA(1V8) = VDD(PLL) = VDDD = VDD(IO) = VDD(sintf) = 1.65 V to 1.95 V; VDDA(3V3) = 3.0 V to 3.6 V; AGND, GND(PLL), DGND and GNDIO are shorted together; Tamb = -40 C to +85 C; typical values measured at VDDA(1V8) = VDD(PLL) = VDDD = VDD(IO) = VDD(sintf) = 1.8 V; VDDA(3V3) = 3.3 V; Tamb = +25 C; RL = 50 ; IO(fs) = 20 mA; maximum sample rate; unless otherwise specified. Symbol VDD(IO) VDDA(3V3) VDDD VDDA(1V8) VDDA(PLL) VDDD(PLL) VDD(sintf) IDD(IO) IDDA(3V3) IDDD IDDA(1V8) Parameter input/output supply voltage analog supply voltage (3.3 V) digital supply voltage analog supply voltage (1.8 V) PLL analog supply voltage PLL digital supply voltage serial interface supply voltage input/output supply current analog supply current (3.3 V) digital supply current. analog supply current, (1.8 V) serial interface supply current digital supply current difference JESD204A compliant fo = 19 MHz; fs = 640 Msps; 2x interpolation; NCO on fo = 19 MHz; fs = 640 Msps; 2x interpolation; NCO on fo = 19 MHz; fs = 640 Msps; 2x interpolation; NCO on including PLL; fo = 19 MHz; NCO on; fs = 640 Msps; 2x interpolation; JESD204A compliant; fo = 19 MHz; fs = 640 Msps; 2x interpolation; NCO on X/sin X function on Conditions Test[1] I I I I I I I I I I I Min 1.65 3.0 1.65 1.65 1.65 1.65 1.65 Typ 1.8 3.3 1.8 1.8 1.8 1.8 1.8 10 43 230 350 Max 1.95 3.6 1.95 1.95 1.95 1.95 1.95 Unit V V V V V V V mA mA mA mA
IDD(sintf)
I
-
83
-
mA
IDDD
I
-
40
-
mA
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
9 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 5. Characteristics ...continued VDDA(1V8) = VDD(PLL) = VDDD = VDD(IO) = VDD(sintf) = 1.65 V to 1.95 V; VDDA(3V3) = 3.0 V to 3.6 V; AGND, GND(PLL), DGND and GNDIO are shorted together; Tamb = -40 C to +85 C; typical values measured at VDDA(1V8) = VDD(PLL) = VDDD = VDD(IO) = VDD(sintf) = 1.8 V; VDDA(3V3) = 3.3 V; Tamb = +25 C; RL = 50 ; IO(fs) = 20 mA; maximum sample rate; unless otherwise specified. Symbol Ptot Parameter Conditions Test[1] C Min Typ tbd Max Unit W total power dissipation fs = 640 Msps; 4x interpolation; NCO off; DAC Q off fs = 640 Msps; 4x interpolation; NCO off fs = 640 Msps; 4x interpolation; NCO on fs = 640 Msps; 2x interpolation; NCO off fs = 640 Msps; 2x interpolation; NCO on fs = 640 Msps; 2x interpolation; NCO Low Power on Power-down mode DAC A and DAC B power-down DAC A, DAC B and JESD204A power down DAC A and DAC B Sleep mode Clock inputs (CLKP, CLKN, CLKINN, CLKINP)[2] Vi Vidth Ri Ci VIL VIH IIL IIH input voltage input differential threshold voltage input resistance input capacitance LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current common-mode input voltage peak-to-peak differential input voltage VIL = 1 V VIH = 2.3 V range, CLK+ or CLK- |Vgpd| < 50 mV[4] |Vgpd| < 50 mV[4] C C D D C C I I 825 -100 GNDIO 0.65 x VDD(IO) 10 0.5 1 1 1575 +100 0.35 x VDD(IO) VDD(IO) mV mV M pF V V A A I I I 0.48 0.17 0.88 W W W
C C C C C
-
1.15 1.19 1.29 1.34 tbd
-
W W W W W
Digital inputs (SDO, SDIO, SCLK, SCS_N, RESET_N)
Digital inputs (Vin_p/Vin_n)[7] VI(cm) VI(dif)(p-p) C C 0.68 175 0.78 1.40 1000 V mV
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
10 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 5. Characteristics ...continued VDDA(1V8) = VDD(PLL) = VDDD = VDD(IO) = VDD(sintf) = 1.65 V to 1.95 V; VDDA(3V3) = 3.0 V to 3.6 V; AGND, GND(PLL), DGND and GNDIO are shorted together; Tamb = -40 C to +85 C; typical values measured at VDDA(1V8) = VDD(PLL) = VDDD = VDD(IO) = VDD(sintf) = 1.8 V; VDDA(3V3) = 3.3 V; Tamb = +25 C; RL = 50 ; IO(fs) = 20 mA; maximum sample rate; unless otherwise specified. Symbol Ztt Zi Parameter Vtt source impedance differential input impedance common-mode output voltage peak-to-peak differential output voltage full-scale output current output voltage output resistance output capacitance DAC monotonicity offset error variation gain error variation reference output voltage reference output current reference output voltage variation auxiliary output current differential outputs auxiliary output voltage auxiliary DAC monotonicity data rate bit rate sampling frequency settling time up to 0.5 LSB D compliance range guaranteed external voltage 1.2 V guaranteed reg value = 00h reg = default value VO Ro Co NDAC(mono) EO EG VO(ref) IO(ref) VO(ref) compliance range C D D D C C I C C C C Conditions Test[1] Min Typ 0.7 100 Max Unit
Digital outputs (SYNC_OUTN/SYNC_OUTP)[3] Vo(cm) Vo(dif)(p-p) 0.79 0.12 0.98 0.48 1.46 0.96 V V
Analog outputs (IOUTAP, IOUTAN, IOUTBP, IOUTBN) IO(fs) D 1.8 tbd 1.6 20 250 3 tbd tbd tbd 1.25 39 131 tbd mA mA k pF bits ppm/C ppm/C V A ppm/C
VDDA(3V3) V
Reference voltage output (GAPOUT)
Analog Auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN) IO(aux) VO(aux) NDAC(aux)mono I C D 0 2.2 10 2 mA V bits
Input timing (Vin_p / Vin_n) fdata fbit fs ts 2x interpolation 4x interpolation serial input Output timing (IOUTAP, IOUTAN, IOUTBP, IOUTBN) 20 650 Msps ns C tbd tbd tbd 325 162.5 3.25 Msps Msps Gbps
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
11 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 5. Characteristics ...continued VDDA(1V8) = VDD(PLL) = VDDD = VDD(IO) = VDD(sintf) = 1.65 V to 1.95 V; VDDA(3V3) = 3.0 V to 3.6 V; AGND, GND(PLL), DGND and GNDIO are shorted together; Tamb = -40 C to +85 C; typical values measured at VDDA(1V8) = VDD(PLL) = VDDD = VDD(IO) = VDD(sintf) = 1.8 V; VDDA(3V3) = 3.3 V; Tamb = +25 C; RL = 50 ; IO(fs) = 20 mA; maximum sample rate; unless otherwise specified. Symbol fNCO fstep fNCO fstep SFDR Parameter NCO frequency step frequency NCO frequency step frequency reg value = 00000000h reg value = F8000000h Dynamic performances spurious-free dynamic fdata = 320 Msps; fs = 640 Msps; BW = fdata / 2 range I fo = 4 MHz at 0 dBFS fo = 19 MHz at 0 dBFS fo = 70 MHz at 0 dBFS fo = 4 MHz at 0 dBFS fo = 19 MHz at 0 dBFS fo = 70 MHz at 0 dBFS SFDRRBW I I I I I
[5]
Conditions reg value = 00000000h reg value = FFFFFFFFh
Test[1] D D D D D D
Min -
Typ 0 640 0.149 0 620 20
Max -
Unit MHz MHz Hz MHz MHz MHz
NCO frequency range; fs = 640 Msps
Low power NCO frequency range; fs = 640 Msps
-75 -70 -63 -75 -70 -76 tbd tbd -78
-
dBc dBc dBc dBc dBc dBc dBc dBc dBc
-
fdata =160 Msps; fs = 640 Msps; BW = fdata / 2
restricted bandwidth fs = 640 Msps, fo = 96 MHz at I spurious-free dynamic 0 dBFS, BW = 40 Mhz range fs = 640 Msps, fo = 150 MHz I at 0 dBFS, BW =100 Mhz third-order intermodulation distortion fo1 = 47 MHz; fo2 = 49 MHz; fs = 320 Msps; 2x interpolation fo1 = 95 MHz; fo2 = 97 MHz; fs = 640 Msps; 4x interpolation fo1 = 159 MHz; fo2 = 161 MHz; fs = 640 Msps; 2x interpolation C
[5]
IMD3
[6]
C
[6]
-
-77
-
dBc
C
[6]
-
-74
-
dBc
ACPR
adjacent channel power ratio
NCO on; 4x interpolation; fs = 614.4 Msps; fo = 115.2 MHz 1 carriers; BW = 5 MHz 2 carriers; BW = 10 MHz 4 carriers; BW = 20 MHz 1 carriers; BW = 5 MHz 2 carriers; BW = 10 MHz 4 carriers; BW = 20 MHz I C C C C C 70 70 67 tbd tbd tbd dB dB dB dB dB dB
NCO on; 2x interpolation; fs = 614.4 Msps; fo = 153.6 MHz
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
12 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 5. Characteristics ...continued VDDA(1V8) = VDD(PLL) = VDDD = VDD(IO) = VDD(sintf) = 1.65 V to 1.95 V; VDDA(3V3) = 3.0 V to 3.6 V; AGND, GND(PLL), DGND and GNDIO are shorted together; Tamb = -40 C to +85 C; typical values measured at VDDA(1V8) = VDD(PLL) = VDDD = VDD(IO) = VDD(sintf) = 1.8 V; VDDA(3V3) = 3.3 V; Tamb = +25 C; RL = 50 ; IO(fs) = 20 mA; maximum sample rate; unless otherwise specified. Symbol NSD Parameter noise spectral density Conditions noise shaper disable noise shaper enable
[1] [2] [3] [4] [5]
Test[1] C C
Min -
Typ -154 -157
Max -
Unit dBm/Hz dBm/Hz
fs = 640 Msps; 8x interpolation; fo = 19 MHz at 0 dBFS
D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested. CLKP / CLKN and CLKINP / CLKINN inputs are at differential LVDS levels. An external termination resistor with a value of between 80 and 120 (see Figure 11) should be connected across the pins. SYNC_OUTP / SYNC_OUTN outputs are differential LVDS outputs. They must be terminated by a resistor with a value of between 80 and 120 . |Vgpd| represents the ground potential difference voltage. This is the voltage that results from current flowing through the finite resistance and the inductance between the receiver and the driver circuit ground voltage. In the band [2.71 MHz foffset < 3.51 MHz], the restricted bandwidth spurious-free dynamic range in a 30 kHz bandwidth is defined as:
f _offset SFDR RBW = - 56 dBc - 15 --------------------- - 2.715 MHz
[6] [7] IMD3 rejection with -6 dBFs/tone. Vin_p and Vin_n inputs are differential CML inputs. There are terminated internally to Vtt via 50 (see Figure 4).
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
13 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
10. Application information
10.1 General description
The DAC1408D650 is a dual 14-bit DAC operating up to 650 Msps. Each DAC consists of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an 8-bit binary weighted sub-DAC. With a maximum input data rate of up to 325 Msps and a maximum output sampling rate of 650 Msps, the DAC1408D650 allows more flexibility for wide bandwidth and multi-carrier systems. Combined with its quadrature modulator and its 32-bit NCO, the DAC1408D650 simplifies the frequency selection of the system. This is also possible because of the 2x or 4x interpolation filters that remove undesired images. DAC1408D650 supports the following JESD204A key features:
* * * * * *
8b/10b decoding, Code group synchronization, Inter-lane alignment, 1+x14+x15 scrambling polynomial, Character replacement, TX/RX synchronization management via SYNC signals.
DAC1408D650 can be interfaced with any logic devices that features high speed SERDES functionality. Such macro is now widely available in FPGA from different vendors. Standalone SERDES ICs can also be used. To enhance the intrinsic board layout simplification of the JESD204A standard, NXP includes polarity swapping for each of the lanes and additionally offers lane swapping. Each physical lane can be configured as being logically lane0 or lane1 or lane2 or lane3. Each DAC generates two complementary current outputs on pins IOUTAP/IOUTAN and IOUTBP/IOUTBN. This provides a full-scale output current of up to 20 mA. An internal reference is available for the reference current which is externally adjustable using pin VIRES. The DAC1408D650 must be configured before operating. Therefore, it features an SPI slave interface to access internal registers. Some of these registers also provide information about the JESD204A interface status. The DAC1408D650 operates at both 3.3 V and 1.8 V each of which has separate digital and analog power supplies. The digital input is 3.3 V compliant and the clock input is LVDS compliant.
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
14 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
10.2 JESD204A receiver
internal configuration interface ILA (Inter-lane Alignment)
8b
SYNC_OUT
10b
RX CONTROLLER
lane#
DES
CLOCK ALIGN
10b
10b
K-DETECT 8b 10b/8b
FA (Frame Assembly)
SYNC AND WORD ALIGN
8b 8b 8b 8b
DESCRAMBLER
14b
14b
frame clock
001aak161
The descrambler can be enabled/disabled
Fig 3.
JESD204A receiver
The JEDEC204A defines the following parameters: L is the number of lanes per link, M is the number of converters per device, F is the number of bytes per frame clock period, The DAC1408D650 supports both LMF = 421 and LMF = 211. The current setting is configurable via the SPI registers interface. The complete Digital Layer Processing adds a variable delay on each lane path. This is mainly due to the inter-lane alignment.
Table 6. td
[1] [2]
Digital Layer Processing Latency Conditions Digital Layer Processing delay Test[2] D Min 13 Typ Max 28 Unit Cycle[1] delay time
Symbol Parameter
Frame clock cycle D = guaranteed by design.
10.2.1 Lane input
Each lane is CML compliant. It is terminated to a common voltage with an integrated 50 resistor.
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Vin_p
50
50
Vin_n
Ztt
Vtt
001aak166
Fig 4.
Lane input termination
The common mode voltage is programmable. See Table 39 "Page 2 register allocation map" for register value. DC coupling is only possible if both DAC and transmitter have the same common mode voltage. Else, AC coupling is required.
VDD1
VDD2
50
50
50
50
50
50
50
50
Zdiff = 100
Zdiff = 100
data in + data in -
data in + data in -
001aak162
001aak163
Fig 5.
DC coupling
Fig 6.
AC coupling
The deserializer performs the incoming data clock recovery and also the serial to parallel conversion. Therefore, each lane includes its own PLL that must first lock. Then the clock alignment module transfers the data from the re-generated clock to the frame clock domain. The frequency of both clocks are the same but the phase relation between the clocks isn't known.
10.2.2 Sync & word align
As stated in JESD204A, transmitter and receiver have to first synchronize. This is achieved through SYNC_OUT signals and SYNC pattern (K28.5 symbol). The receiver (i.e. DAC1408D650) first drives its SYNC outputs. The SYNC signal/pattern is continuously sent until the receiver deasserts the SYNC signal. The Lane Processing makes use of the SYNC-patterns to synchronize the datastream, determine the initial running disparity and to extract the 10 bits word from the incoming datastream (word-alignment).
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The SYNC signal is also used during normal operation by the DAC1408D650 to request a link re-initialization. This occurs when the 8b/10b module loses synchronization. The SYNC_OUT signal conforms to LVDS signaling. Its common mode voltage (see Table 39 "Page 2 register allocation map") and its differential peak to peak amplitude (see Table 39 "Page 2 register allocation map") can be programmed via registers. SYNC_OUT is synchronous with the frame clock.
tFS_R(max) tFS_R(min)
SYNC_OUT
CLK
001aak165
Fig 7. Table 7. td
[1]
SYNC_OUT timing SYNC_OUT timing Conditions frame clock to sync Test[1] C Min tbd Typ Max tbd Unit ns delay time
Symbol Parameter
C = guaranteed by characterization.
10.2.3 K detect & word align
This stage monitors the datastream for code-characters (komma-detect), decodes the words to bytes (octets) and performs optional character-replacement as part of frame/lane alignment monitoring and correction. This module will provide the required control signals to the RX-controller and ILA. This module decodes the 10 bit words into 8 bit words (octets). The decode table is specified in the IEEE Std.802.3-2005 specification (page 41 Table 36 -1a). During decoding, the disparity is calculated according to the disparity rules mentioned in the same specification IEEE Std.802.3-2005 (page 39 chapter 36.2.4.4). When the disparity counter is more than 2 or less than -2, an error will be generated. The following comma symbols are detected during data transmission irrespective of the running disparity: /K/=K28.5 /F/=K28.7 /A/=K28.3 /R/=K28.0 /Q/=K28.4 A flag is sent to the control interface to reflect detected commas in registers. The following flags are also triggered according to the following definitions:
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* VALID: a code group that is found in the column of the 8b/10b decoding tables
according to the current running disparity.
* DISPARITY ERROR: The received code group exists in the 8b/10b decoding table,
but is not found in the proper column according to the current running disparity.
* NOT-IN-TABLE ERROR: The received code group is not found in the 8b/10b decoding
table for either disparity.
* INVALID: a code group that either shows a disparity error or that does not exist in the
8b/10b decoding table. DAC1408D650 supports character replacement whatever the state of the descrambler. When scrambling isn't active, the received K28.3 /A/ or K28.7 /F/ will be replaced by the previous sample. When scrambling is active, the corresponding data octet D28.3 (0xC) or D28.7 (0xFC) will be used.
10.2.4 Descrambler
The used descrambler is the 16-bit parallel self-synchronous descrambler based on the polynomial 1+x14+x15. This processing can be turned off.
10.2.5 Inter lane alignment
This feature removes strict PCB design skew compensation between the lanes. This module handles the alignment of the 4 data streams. Due to interlane-skew and each PLL per lane concept, these alignment characters may be received at different times by the receivers. After the sync period, the lock signal will be high. This enables the receiving of K28.3 /A/ characters. The /A/-characters provided in the initial alignment sequence are then used to align the 4 data streams. With the bit-field sel_ila (2 bits) (refer to Table 65 "Page 4 register allocation map"), one can select the used K28.3 /A/ symbol ("00" => use the 1st /A/ symbol, "01" => use the 2nd /A/ symbol, "10" => use the 3rd /A/ symbol, "11" => use the 4th /A/ symbol) during the initial lane alignment. When all receivers have received their first selected /A/, they start propagating the received data to the frame assembly module at the same point in time. This module can compensate up to +7/-7 frame clock period mis-alignment between the lanes. When initial lane alignment isn't supported the manual alignment mode can be used. After the initial ila sequence, the lane alignment monitoring starts. When a K28.3 /A/ symbol is received among the user data: - its position is compared to the value of the alignment monitor counter, - if 2 successive K28.3 /A/ symbols have been received at a wrong position, a realignment takes place, - if the buffers are empty or overflow, this will be indicated by the registers: buff_err_ln0 .. buff_err_ln3
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10.2.6 Frame assembly
DAC1408D650 supports only /F/ = 1, which means that every frame clock period carries one byte per lane. Frame assembly combines the octet of lane_0 with the 6 msb bits of lane_1 and re-assemble the original 14 bits sample. The same is done for lane_2 and lane_3. Tail bits are dropped. The frame assembler also handles error previously triggered. If scrambling is enabled: If a nit_err (not in table error) or kout_unexp (unexpected control character) occurs in lane_0 and/or lane_1, the previous sample (14 bits) will be repeated 2 times for I (lane_0, lane_1). The same is done for : Q (lane_2, lane_3). If scrambling is disabled: if a nit_err (not in table error) or kout_unexp (unexpected control character) occurs in lane_0 and/or lane_1, the previous sample (14 bits) will be repeated once for I (lane_0, lane_1). The same is done for : Q (lane_2, lane_3).
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SERIAL CLOCK 3.125 GHz encoded octet /10 b9 b8 b7 DESERIALIZER b6 b5 b4 b3 b2 b1 b0 encoded octet /10 b9 b8 b7 DESERIALIZER b6
CHARACTER CLOCK 312.5 MHz
FRAME CLOCK 312.5 MHz /F
scrambled octet S7 S6 S5 10b/8b S4 S3 S2 S1 S0 lane 0
ON/OFF
byte 0 D13 D12 D11 D10 D09 D08 D07 D06 D13 D12 D11
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
scrambled octet S7 S6 S5 10b/8b S4 S3 S2 S1 S0 lane 1
DESCRAMBLER
ON/OFF
byte 1 D05 D04 D03 D02 D01 D00 T FRAME ASSEMBLY T
D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 M = 2 converters D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 DAC1 DAC0
b5 b4 b3 b2 b1 b0 encoded octet
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
DESCRAMBLER
F = 1 byte scrambled octet S7 DESCRAMBLER S6 S5 10b/8b S4 S3 S2 S1 S0 lane 2 ON/OFF byte 2 D13 D12 D11 D10 D09 D08 D07 D06
/10
b9 b8 b7
DESERIALIZER
b6 b5 b4 b3 b2 b1 b0 encoded octet
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
D01 scrambled octet S7 DESCRAMBLER S6 S5 10b/8b S4 S3 S2 S1 S0 lane 3 ON/OFF byte 3 D05 D04 D03 D02 D01 D00 T T
001aak164
/10
b9 b8 b7
D00
DESERIALIZER
b6 b5 b4 b3 b2 b1 b0
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Fig 8.
Frame assembly
10.3 Serial interface (SPI)
10.3.1 Protocol description
The DAC1408D650 serial interface is a synchronous serial communication port allowing easy interfacing with many industry microprocessors. It provides access to the registers that define the operating modes of the chip in both write and read modes.
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This interface can be configured as a 3-wire type (SDIO as bidirectional pin) or a 4-wire type (SDIO and SDO as unidirectional pin, input and output port respectively). In both configurations, SCLK acts as the serial clock, and SCS_N acts as the serial chip select bar. Each read/write operation is sequenced by the SCS_N signal and enabled by a LOW assertion to drive the chip with 2 bytes to 5 bytes, depending on the content of the instruction byte (see Table 9).
RESET_N (optional) SCS_N
SCLK
SDIO SDO (optional)
R/W
N1
N0
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
001aaj812
R/W indicates the mode access, (see Table 8):
Fig 9.
SPI protocol Table 8. R/W 0 1 Read or Write mode access description Description Write mode operation Read mode operation
In Table 9 below, N1 and N0 indicate the number of bytes transferred after the instruction byte.
Table 9. N1 0 0 1 1 Number of bytes to be transferred N0 0 1 0 1 Number of bytes transferred 1 2 3 4
A[4:0]: indicates which register is being addressed. In the case of a multiple transfer, this address concerns the first register after which the next registers follow directly in a decreasing order according to Table 18 "Page 0 register allocation map".
10.3.2 SPI timing description
The SPI interface can operate at a frequency of up to 15 MHz. The SPI timing is shown in Figure 10.
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tw(RESET_N) RESET_N (optional) SCS_N 50 % tsu(SCS_N) 50 % tw(SCLK) SCLK 50 % th(SCS_N)
SDIO
50 % th(SDIO) tsu(SDIO)
001aaj813
Fig 10. SPI timing diagram
The SPI timing characteristics are given in Table 10.
Table 10. Symbol fSCLK tw(SCLK) tsu(SCS_N) th(SCS_N) tsu(SDIO) th(SDIO) tw(RESET_N) SPI timing characteristics Parameter SCLK frequency SCLK pulse width SCS_N set-up time SCS_N hold time SDIO set-up time SDIO hold time RESET_N pulse width Min 30 20 20 10 5 30 Typ Max 15 Unit MHz ns ns ns ns ns ns
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10.4 Clock inputs
DAC1408D650 has two differential clock inputs, namely CLKINN/CLKINP and CLKN/CLKP. They must be driven with signals of exactly the same frequency. As the part has internal clock domain transition circuitry, there is no phase requirement between the two clocks.
Z = 50
CLKP
LVDS
Zdiff = 100
LVDS
Z = 50
CLKN
001aah021
Fig 11. LVDS clock configuration
VDDA(1V8)
1.1 k Z = 50 100 nF
CLKP
55
CML
Zdiff = 100 55 100 nF
LVDS
Z = 50
CLKN
2.2 k
100 nF
AGND
001aah020
Fig 12. Interfacing CML to LVDS
The DAC1408D650 can operate with a clock frequency up to 325 MHz. Both clock inputs can be LVDS (see Figure 11) but they can also be interfaced with CML (see Figure 12). During the reset phase (RESET_N asserted), both clocks must be stable and running. This ensures proper reset of the complete device.
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10.5 FIR Filters
The two interpolation FIR filters have a stop band attenuation of at least 80 dBc and a pass band ripple of less than 0,0005 dB.
Table 11. Lower H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) H(20) H(21) H(22) H(23) H(24) H(25) H(26) H(27) H(28) Interpolation filter coefficients Second interpolation filter Value -4 0 13 0 -34 0 72 0 -138 0 245 0 -408 0 650 0 -1003 0 1521 0 -2315 0 3671 0 -6642 0 20756 32768 Lower H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) Upper H(23) H(22) H(21) H(20) H(19) H(18) H(17) H(16) H(15) H(14) H(13) Value -2 0 17 0 -75 0 238 0 -660 0 2530 4096 Upper H(55) H(54) H(53) H(52) H(51) H(50) H(49) H(48) H(47) H(46) H(45) H(44) H(43) H(42) H(41) H(40) H(39) H(38) H(37) H(36) H(35) H(34) H(33) H(32) H(31) H(30) H(29)
First interpolation filter
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10.6 Quadrature modulator and Numerically Controlled Oscillator (NCO)
The quadrature modulator allows the 14-bit I and Q data to be mixed with the carrier signal generated by the NCO. The frequency of the NCO is programmed over 32-bit and allows the sign of the sine component to be inverted in order to operate positive or negative, lower or upper single sideband up-conversion.
10.6.1 NCO in 32-bit
When using the NCO, the frequency can be set by the four registers FREQNCO_LSB, FREQNCO_LISB, FREQNCO_UISB and FREQNCO_MSB over 32 bits. The frequency for the NCO in 32-bit is calculated as follows: M x fs f NCO = ---------------32 2 where M is the decimal representation of FREQ_NCO[31:0]. The phase of the NCO can be set from 0 to 360 by both registers PHINCO_LSB and PHINCO_MSB over 16 bits. The default setting is fNCO = 96 MHz when fs = 640 Msps and the default phase is 0. (1)
10.6.2 Low-power NCO
When using the low-power NCO, the frequency can be set by the 5 MSB of register FREQNCO_MSB. The frequency for the low-power NCO is calculated as follows: M x fs f NCO = ---------------5 2 where M is the decimal representation of FREQ_NCO[31:27]. The phase of the low-power NCO can be set by the 5 MSB of the register PHINCO_MSB. (2)
10.6.3 Minus 3dB
During normal use, a full-scale pattern will also be full scale at the output of the DAC. Nevertheless, when the I and Q data are simultaneously close to full scale, some clipping can occur and the Minus_3dB function can be used to reduce the gain by 3 dB in the modulator. This is to keep a full-scale range at the output of the DAC without added interferers.
10.7 x / (sin x)
Due to the roll-off effect of the DAC, a selectable FIR filter is inserted to compensate for the (sin x) / x effect. This filter introduces a DC loss of 3.4 dB. The coefficients are represented in Table 12 "Inversion filter coefficients".
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Inversion filter coefficients Upper H(9) H(8) H(7) H(6) Value 2 -4 10 -35 401
Table 12. Lower H(1) H(2) H(3) H(4) H(5)
First interpolation filter
10.8 DAC transfer function
The full-scale output current for each DAC is the sum of the two complementary current outputs: I O ( fs ) = I IOUTP + I IOUTN The output current depends on the digital input data: DATA I IOUTP = I O ( fs ) x --------------- 16383 16383 - DATA I IOUTN = I O ( fs ) x ------------------------------------ - 16383 (4) (5) (3)
The setting applied to CODING (register 00h[2]; see Table 18 "Page 0 register allocation map") defines whether the DAC1408D650 operates with a binary input or a two's complement input. Table 13 "DAC transfer function" shows the output current as a function of the input data, when IO(fs) = 20 mA.
Table 13. Data 0 ... 8192 ... 16383 DAC transfer function I13/Q13 to I0/Q0 Binary 00 0000 0000 0000 ... 10 0000 0000 0000 ... 11 1111 1111 1111 Two's complement 10 0000 0000 0000 ... 00 0000 0000 0000 ... 01 1111 1111 1111 0 mA ... 10 mA ... 20 mA 20 mA ... 10 mA ... 0 mA IOUTP IOUTN
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10.9 Full-scale current
10.9.1 Regulation
Figure 13 shows the internal configuration. The DAC1408D650 reference circuitry integrates an internal bandgap reference voltage which delivers a 1.25 V reference to the GAPOUT pin. It is recommended to decouple pin GAPOUT using a 100 nF capacitor. The reference current is generated via an external resistor of 910 (1 %) connected to pin VIRES. A control amplifier sets the appropriate full-scale current (IO(fs)) for both DACs (see Figure 13 "Internal reference configuration").
REF. BANDGAP
100 nF
AGND
910 (1 %)
GAPOUT
AGND
VIRES
DAC CURRENT SOURCES ARRAY
001aaj816
Fig 13. Internal reference configuration
This configuration is optimum for temperature drift compensation because the bandgap reference voltage can be matched to the voltage across the feedback resistor. 10.9.1.1 External regulation The DAC current can also be set by applying an external reference voltage to the non-inverting input pin GAPOUT and disabling the internal bandgap reference voltage with GAP_PD (register 00h[0]; see Table 19 "COMMON register (address 00h) bit description").
10.9.2 Full-scale current adjustment
The default full-scale current (IO(fs)) is 20 mA but further adjustments can be made by the user to both DACs independently via the serial interface from 1.6 mA to 22 mA, +/- 10 %. The settings applied to DAC_A_GAIN_COARSE[3:0] (register 0Ah; see Table 29 "DAC_A_CFG_2 register (address 0Ah) bit description" and register 0Bh; see Table 30 "DAC_A_CFG_3 register (address 0Bh) bit description") and to DAC_B_GAIN COARSE[3:0] (register 0Dh; see Table 32 "DAC_B_CFG_2 register (address 0Dh) bit description" and register 0Eh; see Table 33 "DAC_B_CFG_3 register (address 0Eh) bit description") define the coarse variation of the full-scale current (see Table 14 "IO(fs) coarse adjustment").
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Table 14. IO(fs) coarse adjustment Default settings are shown highlighted. DAC_GAIN_COARSE[3:0] Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Binary 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1.6 3.0 4.4 5.8 7.2 8.6 10.0 11.4 12.8 14.2 15.6 17.0 18.5 20.0 21.0 22.0 IO(fs) (mA)
The settings applied to DAC_A_GAIN_FINE[5:0] (register 0Ah; see Table 29 "DAC_A_CFG_2 register (address 0Ah) bit description") and to DAC_B_GAIN_FINE[5:0] (register 0Dh; see Table 32 "DAC_B_CFG_2 register (address 0Dh) bit description") define the fine variation of the full-scale current (see Table 15 "IO(fs) fine adjustment").
Table 15. IO(fs) fine adjustment Default settings are shown highlighted. DAC_GAIN_FINE[5:0] Decimal -32 ... 0 ... 31 Two's complement 10 0000 ... 00 0000 ... 01 1111 -10 % ... 0 ... +10 % Delta IO(fs)
The coding of the fine gain adjustment is two's complement.
10.10 Digital offset adjustment
When the DAC1408D650 analog output is DC connected to the next stage, the digital offset correction can be used to adjust the common mode level at the output of the DAC. It adds an offset at the end of the digital part, just before the DAC. The settings applied to DAC_A_OFFSET[11:0] (register 09h; see Table 28 "DAC_A_CFG_1 register (address 09h) bit description" and register 0Bh; see Table 30 "DAC_A_CFG_3 register (address 0Bh) bit description") and to "DAC_B_OFFSET[11:0]"
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(register 0Ch; see Table 31 "DAC_B_CFG_1 register (address 0Ch) bit description" and register 0Eh; see Table 33 "DAC_B_CFG_3 register (address 0Eh) bit description") define the range of variation of the digital offset (see Table 16 "Digital offset adjustment").
Table 16. Digital offset adjustment Default settings are shown highlighted. DAC_OFFSET[11:0] Decimal -2048 -2047 ... -1 0 +1 ... 2046 2047 Two's complement 1000 0000 0000 1000 0000 0001 ... 1111 1111 1111 0000 0000 0000 0000 0000 0001 ... 0111 1111 1110 0111 1111 1111 -4096 -4094 ... -2 0 +2 ... +4092 +4094 Offset applied
10.11 Analog output
The DAC1408D650 has two output channels each of which produces two complementary current outputs. These allow the even-order harmonics and noise to be reduced. The pins are IOUTAP/IOUTAN and IOUTBP/IOUTBN respectively and need to be connected via a load resistor RL to the 3.3 V analog power supply (VDDA(3V3)). For the equivalent analog output circuit of one DAC, refer to Figure 14 "Equivalent analog output circuit (one DAC)". This circuit consists of a parallel combination of NMOS current sources, and their associated switches, for each segment.
VDDA(3V3)
RL
RL
IOUTAP/IOUTBP IOUTAN/IOUTBN
AGND
AGND
001aah019
Fig 14. Equivalent analog output circuit (one DAC)
The cascode source configuration increases the output impedance of the source, thus improving the dynamic performance of the DAC by introducing less distortion. The device can provide an output level of up to 2 Vo(p-p) depending on the application, the following stages and the targeted performances.
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10.12 Auxiliary DACs
The DAC1408D650 integrates 2 auxiliary DACs that can be used to compensate for any offset between the DAC and the next stage in the transmission path. Both auxiliary DACs have a resolution of 10-bit and are current sources (referenced to ground). I O ( AUX ) = I AUXP + I AUXN The output current depends on the auxiliary DAC data: AUX [ 9:0 ] AUXP = I O ( AUX ) x ------------------------- 1023 (1023 - A UX [ 9:0 ] ) AUXN = I O ( AUX ) x --------------------------------------------- - 1023 Table 17 "Auxiliary DAC transfer function" shows the output current as a function of the auxiliary DAC data.
Table 17. Auxiliary DAC transfer function Default settings are shown highlighted. Data 0 ... 512 ... 1023 AUX[9:0] (binary) 00 0000 0000 ... 10 0000 0000 ... 11 1111 1111 IAUXP 0 mA ... 1.1 mA ... 2.2 mA IAUXN 2.2 mA ... 1.1 mA ... 0 mA
(6)
(7) (8)
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10.13 Output configuration
10.13.1 Basic output configuration
The use of a differentially-coupled transformer output provides optimum distortion performance (see Figure 15 "1 Vo(p-p) differential output with transformer"). In addition, it helps to match the impedance and provides electrical isolation.
3.3 V
50 2:1
0 mA to 20 mA IOUTP 0 mA to 20 mA IOUTN
50
50
3.3 V IOUTP/IOUTN Vo(cm) = 2.8 V Vo(dif)(p-p) = 1 V
001aaj817
Fig 15. 1 Vo(p-p) differential output with transformer
The DAC1408D650 can operate up to 2 Vo(p-p) differential outputs. In this configuration, it is recommended to connect the center tap of the transformer to a 62 resistor connected to the 3.3 V analog power supply, in order to adjust the DC common mode to approximately 2.7 V (see Figure 16 "2 Vo(p-p) differential output with transformer").
3.3 V
3.3 V
62 4:1
100
0 mA to 20 mA IOUTP 0 mA to 20 mA IOUTN
100 50
3.3 V IOUTP/IOUTN Vo(cm) = 2.7 V Vo(dif)(p-p) = 2 V
001aaj818
Fig 16. 2 Vo(p-p) differential output with transformer
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DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
10.13.2 DC interface to an Analog Quadrature Modulator (AQM)
When the system operation requires to keep the DC component of the spectrum, the DAC1408D650 can use a DC interface to connect to an AQM. In this case, the offset compensation for LO cancellation can be made with the use of the digital offset control in the DAC. Figure 17 provides an example of a connection to an AQM with a 1.7 Vi(cm) common mode input level.
3.3 V
AQM (Vi(cm) = 1.7 V)
51.1
51.1 442
IOUTP
442
BBP BBN 0 mA to 20 mA
768 768
IOUTN
IOUTP/IOUTN Vo(cm) = 2.67 V Vo(dif)(p-p) = 1.98 V
BBP/BBN Vi(cm) = 1.7 V Vi(dif)(p-p) = 1.26 V
001aaj541
Fig 17. An example of a DC interface to a 1.7 Vi(cm) AQM
Figure 18 provides an example of a connection to an AQM with a 3.3 Vi(cm) common mode input level.
3.3 V
5V
AQM (Vi(cm) = 3.3 V)
54.9
54.9 237
750
750
IOUTP
237
BBP BBN
1.27 k 1.27 k
IOUTN
IOUTP/IOUTN Vo(cm) = 2.75 V Vo(dif)(p-p) = 1.97 V
BBP/BBN Vi(cm) = 3.3 V Vi(dif)(p-p) = 1.5 V
001aaj542
Fig 18. An example of a DC interface to a 3.3 Vi(cm) AQM
The auxiliary DACs can be used to control the offset in a precise range or with precise steps. Figure 19 provides an example of a DC interface with the auxiliary DACs to an AQM with a 1.7 Vi(cm) common mode input level.
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NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
3.3 V
AQM (Vi(cm) = 1.7 V)
51.1
51.1 442
IOUTP
442
BBP BBN 0 mA to 20 mA
698 698
IOUTN
AUXP AUXN 1.1 mA (typ.)
51.1 51.1
IOUTP/IOUTN Vo(cm) = 2.67 V Vo(dif)(p-p) = 1.94 V
BBP/BBN Vi(cm) = 1.7 V Vi(dif)(p-p) = 1.23 V offset correction up to 36 mV
001aaj543
Fig 19. An example of a DC interface to a 1.7 Vi(cm) AQM when using auxiliary DACs
Figure 20 provides an example of a DC interface with the auxiliary DACs to an AQM with a 3.3 Vi(cm) common mode input level.
3.3 V
5V
AQM (Vi(cm) = 3.3 V)
54.9
54.9 237
750
750
IOUTP
237
BBP BBN
634 k 634 k
IOUTN
AUXP AUXN
442 k 442 k
IOUTP/IOUTN Vo(cm) = 2.75 V Vo(dif)(p-p) = 1.96 V
BBP/BBN Vi(cm) = 3.3 V Vi(dif)(p-p) = 1.5 V offset correction up to 36 mV
001aaj544
Fig 20. An example of a DC interface to a 3.3 Vi(cm) AQM when using auxiliary DACs
The constraints to adjust the interface are the output compliance range of the DAC and the auxiliary DACs, the input common mode level of the AQM, and the range of offset correction.
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DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
10.13.3 AC interface to an Analog Quadrature Modulator (AQM)
When the AQM common mode voltage is close to ground, the DAC1408D650 must be AC-coupled and the auxiliary DACs are needed for offset correction. Figure 20 provides an example of a connection to an AQM with a 0.5 Vi(cm) common mode input level when using auxiliary DACs.
3.3 V
5V
AQM (Vi(cm) = 0.5 V)
66.5
66.5 10 nF
2 k
2 k
IOUTP
10 nF
BBP BBN 0 mA to 20 mA
174 174
IOUTN
AUXP AUXN 1.1 mA (typ.)
34 34
IOUTP/IOUTN Vo(cm) = 2.65 V Vo(dif)(p-p) = 1.96 V
BBP/BBN Vi(cm) = 0.5 V Vi(dif)(p-p) = 1.96 V offset correction up to 70 mV
001aaj589
Fig 21. An example of an AC interface to a 0.5 Vi(cm) AQM when using auxiliary DACs
10.14 Power and grounding
In order to obtain optimum performance, it is recommended that the 1.8 V analog power supplies on pins 5, 11, 71, 77 and 99 should not be connected with the ones on pins 6, 70, 79, 81, 83, 93, 95 and 97 on the top layer. To optimize the decoupling, the power supplies should be decoupled with the following ground pins:
* VDDD(1V8): pin 18 with 19 and pin 55 with 54. * VDD(IO)(3V3): pin 14 with 15 and pin 60 with 61. * VDDA(1V8): pin 5 with 4; pin 6 with pin 7; pin 11 with 10; pin 71 with 72; pin 77 with 78;
pins 79, 81, 83 with 80, 82, 84; pins 93, 95, 97 with 92, 94, 96 and pin 99 with 98.
* VDDA(3V3): pin 1 with 100 and pin 75 with 76. * VDDA(sintf)(1V8): pin 26 with 29; pin 32 with pin 35 and pin 38; pin 41 with pin 38 and
pin 44.
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DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
10.15 Configuration interface
10.15.1 Register description
DAC1408D650 implements indirect addressing using a page access method. The page-address is located at address 0x1F and is by default 0x00, which selects page_0 as default-page. For example, to access registers which configure the jesdrx, one must first activate page_4 by writing 0x04 to the page-address 0x1F. The DAC1408D650 contains 6 different pages.
10.15.2 Detailed descriptions of registers
The register information has been provided in page form accompanied by a detailed description for each bit in the tables following the register allocation map of each page.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 10.15.2.1 Page 0 allocation map description
Table 18. Page 0 register allocation map R/W Bit definition b7 0 1 2 3 4 5 6 7 8 9 00h COMMON 01h TXCFG 02h PLLCFG 03h FREQNCO_LSB 04h FREQNCO_LISB 05h FREQNCO_UISB 06h FREQNCO_MSB 07h PHINCO_LSB 08h PHINCO_MSB 09h DAC_A_CFG_1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DAC_A_PD DAC_A_SLEEP DAC_A_GAIN_COARSE[7:6] DAC_A_GAIN_COARSE[9:8] DAC_B_PD DAC_B_SLEEP DAC_B_GAIN_COARSE[7:6] DAC_B_GAIN_COARSE[9:8] DAC_A_AUX[9:2] DAC_B_AUX[9:2] PAGE DAC_B_AUX[1:0] DAC_A_AUX[1:0] SPI_3W NCO_EN PD_PLL b6 SPI_RST b5 b4 b3 INTERLEAVED_ MODE MODE[2:0] PLL_DIV[1:0] b2 DF b1 PD_ALL b0 PD_GAP Default Bin Hex 10001100 8Ch 00000001 01h 00000000 00h 01100110 66h 01100110 66h 01100110 66h 00100110 26h 00000000 00h 00000000 00h
Objective data sheet Rev. 01 -- 26 May 2009 36 of 88
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NXP Semiconductors
Address Register name
NCO_LOWPOW INV_SINE_EN ER_SEL PD_PLL_IO
INT_FIR[1:0] PLL_PHASE_SEL [1:0] PLL_POL
FREQ_NCO[7:0] FREQ_NCO[15:18] FREQ_NCO[23:16] FREQ_NCO[31:24] PHI_NCO[7:0] PHI_NCO[15:8] DAC_A_OFFSET[5:0] DAC_A_GAIN_FINE[5:0] DA_A_OFFSET[11:6] DAC_B_OFFSET[5:0] DAC_B_GAIN_FINE[5:0] DA_B_OFFSET[11:6] -
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
00000000 00h 01000000 40h 11000000 C0h 00000000 00h 11000000 40h 11000000 C0h
10 0Ah DAC_A_CFG_2 11 0Bh DAC_A_CFG_3 12 0Ch DAC_B_CFG_1 13 0Dh DAC_B_CFG_2 14 OEh DAC_B_CFG_3 15 OFh DAC_CFG
MINUS3DB NOISESHA 11000000 00h PER 10000000 80h 00000000 00h 10000000 80h 00000000 00h 00000000 00h
26 1Ah DAC_A_AUX_MSB R/W 27 1Bh DAC_A_AUX_LSB R/W DAC_A_AUX_PD 28 1Ch DAC_B_AUX_MSB R/W 29 1Dh DAC_B_AUX_LSB R/W DAC_B_AUX_PD 31 1Fh PAGE_ADDRESS R/W
DAC1408D650
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
10.15.2.2
Page 0 bit definition detailed description Please refer to Table 18 for a register overview for page 0. In the following tables, all the values emphasized in bold are the default values.
Table 19. COMMON register (address 00h) bit description Default settings are shown highlighted. Bit 7 Symbol SPI_3W Access Value Description R/W 0 1 6 SPI_RST R/W 0 1 3 INTERLEAVED_MODE R/W 0 1 2 DF R/W 0 1 1 PD_ALL R/W 0 1 0 GAP_PD R/W 0 1 serial interface bus type 4 wire SPI 3 wire SPI serial interface reset no reset performs a reset on all registers except 0x00 state disabled enabled data format unsigned format signed (two's compliment) format power-down no action all circuits (digital and analog) are switched off internal bandgap power-down no action internal bandgap references are switched off
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DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 20. TXCFG register (address 01h) bit description Default settings are shown highlighted. Bit 7 Symbol NCO_EN Access Value Description R/W 0 1 6 NCO_LP_SEL R/W 0 1 5 INV_SINE_EN R/W 0 1 4 to 2 MODE[2:0] R/W 000 001 010 011 100 1 to 0 INT_FIR[1:0] R/W 00 01 10 NCO disabled (the NCO phase is reset to 0) enabled low-power NCO NCO may use all 32 bits NCO frequency and phase given by the five MSBs of the registers 06h and 08h respectively x / (sin x) function disabled enabled modulation dual DAC: no modulation positive upper single sideband up-conversion positive lower single sideband up-conversion negative upper single sideband up-conversion negative lower single sideband up-conversion interpolation no interpolation 2x 4x 8x
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DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 21. PLLCFG register (address 02h) bit description Default settings are shown highlighted. Bit 7 Symbol PLL_PD Access R/W 0 1 6 5 PLL_DIV_PD R/W R/W 0 1 4 to 3 PLL_DIV[1:0] R/W 00 01 2 to 1 PLL_PHASE[1:0] R/W 00 01 10 0 PLL_POL R/W 0 1 Table 22. Bit 7 to 0 Value Description PLL switched on switched off undefined PLL divider switched on switched off PLL divider factor 2 4 8 PLL phase shift of fs 0 120 240 clock edge of DAC (fs) normal inverted
FREQNCO_LSB register (address 03h) bit description Access Value Description R/W lower 8-bits for the NCO frequency setting
Symbol FREQ_NCO[7:0]
Table 23. Bit 7 to 0
FREQNCO_LISB register (address 04h) bit description Access Value Description R/W lower intermediate 8-bits for the NCO frequency setting
Symbol FREQ_NCO[15:8]
Table 24. Bit 7 to 0
FREQNCO_UISB register (address 05h) bit description Access Value Description R/W upper intermediate 8-bits for the NCO frequency setting
Symbol FREQ_NCO[23:16]
Table 25. Bit 7 to 0
FREQNCO_MSB register (address 06h) bit description Access Value Description R/W most significant 8-bits for the NCO frequency setting
Symbol FREQ_NCO[31:24]
Table 26. Bit 7 to 0
PHINCO_LSB register (address 07h) bit description Access Value Description R/W lower 8-bits for the NCO phase setting
Symbol PH_NCO[7:0]
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DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
PHINCO_MSB register (address 08h) bit description Access Value Description R/W most significant 8-bits for the NCO phase setting
Table 27. Bit 7 to 0
Symbol PH_NCO[15:8]
Table 28. DAC_A_CFG_1 register (address 09h) bit description Default settings are shown highlighted. Bit 7 Symbol DAC_A_PD Access Value Description R/W 0 1 6 DAC_A_SLEEP R/W 0 1 5 to 0 DAC_A_OFFSET[5:0] R/W DAC A power on off DAC A Sleep mode disabled enabled lower 6-bits for the DAC A offset
Table 29. Bit 7 to 6 5 to 0
DAC_A_CFG_2 register (address 0Ah) bit description Access Value Description least significant 2-bits for the DAC A gain setting for coarse adjustment lower 6-bits for the DAC A gain setting for fine adjustment
Symbol
DAC_A_GAIN_COARSE[7:6] R/W DAC_A_GAIN_FINE[5:0] R/W
Table 30. Bit 7 to 6 5 to 0
DAC_A_CFG_3 register (address 0Bh) bit description Access Value Description most significant 2-bits for the DAC A gain setting for coarse adjustment most significant 6-bits for the DAC A offset
Symbol
DAC_A_GAIN_COARSE[9:8] R/W DAC_A_OFFSET[11:6] R/W
Table 31. DAC_B_CFG_1 register (address 0Ch) bit description Default settings are shown highlighted. Bit 7 Symbol DAC_B_PD Access Value Description R/W 0 1 6 DAC_B_SLEEP R/W 0 1 5 to 0 DAC_B_OFFSET[5:0] R/W DAC B power on off DAC B Sleep mode disabled enabled lower 6-bits for the DAC B offset
Table 32. Bit 7 to 6 5 to 0
DAC_B_CFG_2 register (address 0Dh) bit description Access Value Description less significant 2-bits for the DAC B gain setting for coarse adjustment the 6-bits for the DAC B gain setting for fine adjustment
(c) NXP B.V. 2009. All rights reserved.
Symbol
DAC_B_GAIN_COARSE[7:6] R/W DAC_B_GAIN_FINE[5:0] R/W
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NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
DAC_B_CFG_3 register (address 0Eh) bit description Access Value Description most significant 2-bits for the DAC B gain setting for coarse adjustment most significant 6-bits for the DAC B offset
Table 33. Bit 7 to 6 5 to 0
Symbol
DAC_B_GAIN_COARSE[9:8] R/W DAC_B_OFFSET[11:6] R/W
Table 34. DAC_CFG register (address 0Fh) bit description Default settings are shown highlighted. Bit 1 Symbol MINUS_3DB Access Value R/W 0 1 0 NOISE_SHAPER R/W 0 1 Table 35. Bit 7 to 0 Description NCO gain unity -3 dB noise shaper disabled enabled
DAC_A_Aux_MSB register (address 1Ah) bit description Access Value R/W Description most significant 8-bits for the auxiliary DAC A
Symbol AUX_A[9:2]
Table 36. DAC_A_Aux_LSB register (address 1Bh) bit description Default settings are shown highlighted. Bit 7 Symbol AUX_A_PD Access Value R/W 0 1 1 to 0 Table 37. Bit 7 to 0 AUX_A[1:0] R/W Description auxiliary DAC A power on off lower 2-bits for the auxiliary DAC A
DAC_B_Aux_MSB register (address 1Ch) bit description Symbol AUX_B[9:2] Access Value R/W Description most significant 8-bits for the auxiliary DAC B
Table 38. DAC_B_Aux_LSB register (address 1Dh) bit description Default settings are shown highlighted. Bit 7 Symbol AUX_B_PD Access Value R/W 0 1 1 to 0 AUX_B[1:0] R/W Description auxiliary DAC B power on off lower 2-bits for the auxiliary DAC B
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 10.15.2.3 Page 2 allocation map description
Table 39. Page 2 register allocation map R/W Bit definition b7 0 1 00h MAINCONTROL 01h MAN_PON R/W R/W b6 b5 FULL RE_INIT b4 FULL RE_INIT b3 b2 b1 b0 Default Bin Hex MAN_PON_ MAN_SUPD_ FORCE_RES FORCE_RE 00000011 03h CNTR CNTR ET_DCLK SET_FCLK
Objective data sheet Rev. 01 -- 26 May 2009 42 of 88
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NXP Semiconductors
Address Register name
MAN_PON_ MAN_PON_ MAN_PON_L MAN_PON_L MAN_PON_L MAN_PON_ 00000000 00h CLKBUFFE ALL N3 N2 N1 LN0 R
2
02h MAN_SUPD
R/W MAN_PLL MAN_PLL MAN_PLL_ MAN_PLL_S MAN_PLL_S MAN_PLL_S MAN_PLL_S MAN_PLL_S 00000000 00h _SEL_PD _SEL_PD SEL_PD_LN EL_PD_LN0 TARTUP_LN TARTUP_LN TARTUP_LN TARTUP_LN _LN3 _LN2 1 3 2 1 0 RST_EXT_FCLK_TIME[7:0] RST_EXT_DCLK_TIME[7:0] DCSMU PREDIVIDER[7:0] PLL_CHARGE_TIME[7:0] PLL_RUNIN_TIME[7:0] 00111111 3Fh 00100000 20h 00011110 1Eh 00110010 32h 00110010 32h 00000100 04h QLEV_CNTRL[1:0] IQ_DC_LEVEL[7:0] SET_SYNC_LEVEL[3:0] JD_MODE CDI_MODE SR_CDI SET_ICHP_PD1[3:0] SET_ICHP_PD2[3:0] SET_ICHP_PFD[3:0] SET_RATIO_PD1[3:0] SET_RATIO_PD2[3:0] SET_RATIO_PFD[3:0] SET_VCM[2:0] IQ_DC_LEVEL[11:9] 01011000 58h 00000000 00h 00000001 01h 00000001 01h 00000001 01h 00000010 02h 00001000 08h 00000110 06h 00000010 02h 01000011 43h 00000100 04h
4 5 6 7 8 9
04h RST_EXT_FCLK R/W 05h RST_EXT_DCLK R/W 06h DCSMU_PREDIV R/W CNT 07h PLL_CHARGETI R/W ME 08h PLL_RUN_IN_TI R/W ME 09h CA_RUN_IN_TIM R/W CA_RUNIN_TIME[7:0] E ILEV_CNTRL[1:0]
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
10 0Ah IQ_LEVEL_CNTR R/W L 11 0Bh IQ_DC_LEVEL_L R/W SB 16 10h SET_ICHP_PD1 17 11h SET_ICHP_PD2 R/W R/W
DAC1408D650
18 12h SET_ICHP_PFD R/W 19 13h SET_RATIO_PD1 R/W 20 14h SET_RATIO_PD2 R/W 21 15h SET_RATIO_PFD R/W 22 16h SET_VCM_VOLT R/W AGE 23 17h SET_SYNC 26 1Ah MISC_CNTRLS R/W -
R/W SET_SYNC_VCOM[3:0] -
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 39. Page 2 register allocation map ...continued R/W Bit definition b7 29 1Dh DIG_VERSION R 30 1Eh JRX_ANA_VERSI R ON b6 b5 b4 b3 b2 b1 b0 DIG_VERSION_ID[7:0] JRX_ANA_VERSION_ID[7:0] Default Bin Hex 11010000 D0h 00000001 01h 00000000 00h
Objective data sheet Rev. 01 -- 26 May 2009
(c) NXP B.V. 2009. All rights reserved. DAC1408D650_1
NXP Semiconductors
Address Register name
31 1Fh PAGE_ADDRESS R/W PAGE
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
DAC1408D650
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DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
10.15.2.4
Page 2 bit definition detailed description Please refer to Table 39 for a register overview and their default values. In the following tables, all the values emphasized in bold are the default values.
Table 40. MAINCONTROL register (address 00h) bit description Default settings are shown highlighted. Bit 5 Symbol FULL_RE_INIT Access Value Description R/W 1 0 4 SYNC_INIT_LEVEL R/W 0 1 3 MAN_PON_CNTRL R/W 1 0 2 MAN_SUPD_CNTRL R/W 0 1 1 FORCE_RESET_DCLK R/W 0 1 0 FORCE_RESET_FCLK R/W 0 1 initialization full re-initialization quick re-initialization sync sync starts with '0' sync starts with '1' pon manual control of pon's pon's jesdrx module controlled by dcsmu BangBang PLL run-in timing BangBang PLL controlled by dcsmu manual control of run-in timing BangBang PLL reset_dcl release reset_dclk force reset_dclk reset_fclk release reset_fclk force reset_fclk
Table 41. MAN_PON register (address 01h) bit description Default settings are shown highlighted. Bit 5 4 3 2 1 0 Symbol MAN_PON_ALL MAN_PON_LN3 MAN_PON_LN2 MAN_PON_LN1] MAN_PON_LN0 Access Value Description pon_clkbuffer (when man_pon_cntrl = 1) pon_all (when man_pon_cntrl = 1) pon_ln3 (when man_pon_cntrl = 1) pon_ln2 (when man_pon_cntrl = 1 pon_ln1 (when man_pon_cntrl = 1) pon_ln0 (when man_pon_cntrl = 1) R/W R/W R/W R/W R/W MAN_PON_CLKBUFFER R/W
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DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 42. MAN_SUPD register (address 02h) bit description Default settings are shown highlighted. Bit 7 6 5 4 3 2 1 0 Symbol MAN_PLL_SEL_PD_LN3 MAN_PLL_SEL_PD_LN2 MAN_PLL_SEL_PD_LN1 MAN_PLL_SEL_PD_LN0 MAN_PLL_STARTUP_LN3 MAN_PLL_STARTUP_LN2 MAN_PLL_STARTUP_LN1 MAN_PLL_STARTUP_LN0 Access R/W R/W R/W R/W R/W R/W R/W R/W Value Description sel_pd_ln3 (when man_supd_cntrl = 1) sel_pd_ln2 (when man_supd_cntrl = 1) sel_pd_ln1 (when man_supd_cntrl = 1) sel_pd_ln0 (when man_supd_cntrl = 1) startup_ln3 (when man_supd_cntrl = 1) startup_ln2 (when man_supd_cntrl = 1) startup_ln1 (when man_supd_cntrl = 1) startup_ln0 (when man_supd_cntrl = 1)
Table 43. Bit 7 to 0
RST_EXT_FCLK register (address 04h) bit description Access Value Description R/W 3Fh specifies extension-time reset_fclk in fclk periods
Symbol RST_EXT_FCLK[7:0]
Table 44. Bit
RST_EXT_DCLK register (address 05h) bit description Access Value Description 20h specifies extension-time reset_dclk (in dclk-periods)
Symbol
7 to 0 RST_EXT_DCLK[7:0] R/W
Table 45. Bit 7 to 0
DCSMU_PREDIVCNT register (address 06h) bit description Access Value Description R/W 1Eh value used by dcsmu predivider (at fclk)
Symbol DCSMU_PREDIVCNT[7:0]
Table 46. Bit 7 to 0
PLL_CHARGETIME register (address 07h) bit description Access Value Description R/W 32h PLL chargetime (at fclk/predivcnt; startup)
Symbol PLL_CHARGE_TIME[7:0]
Table 47. Bit 7 to 0
PLL_RUN_IN_TIME register (address 08h) bit description Access Value Description 32h PLL run in time (at fclk/predivcnt; sel_pd)
Symbol
PLL_RUNIN_TIME[7:0] R/W
Table 48. Bit 7 to 0
CA_RUN_IN_TIME register (address 09h) bit description Access Value Description 04h clock alignment run in time (at fclk/predivcnt)
Symbol
CA_RUNIN_TIME[7:0] R/W
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Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 49. IQ_LEVEL_CNTRL register (address 0Ah) bit description Default settings are shown highlighted. Bit 7 to 6 Symbol ILEV_CNTRL[1:0] Access Value Description R/W 0 1 I_IN <= DATA_I_CDI I_IN <= DATA_I_CDI when EN_DATA_I_CDI='1' else 1X: I_IN <= IQ_DC_LEVEL x 4 Q_IN <= DATA_Q_CDI Q_IN <= DATA_Q_CDI when EN_DATA_Q_CDI='1' else 1X: Q_IN <= IQ_DC_LEVEL X 4 msb's iq dc level
5 to 4
QLEV_CNTRL[1:0]
R/W 0 1
3 to 0
IQ_DC_LEVEL[11:9]
R/W
-
Table 50. Bit 7 to 0
IQ_DC_LEVEL_LSB register (address 0Bh) bit description Access Value Description R/W lsb's iq dc level
Symbol IQ_DC_LEVEL[7:0]
Table 51. Bit 3 to 0
SET_ICHP_PD1 register (address 10h) bit description Access Value R/W Description integrating charge pump pd ( error < 45 deg.)
Symbol SET_ICHP_PD1[3:0]
Table 52. SET_ICHP_PD2 register (address 11h) bit description Default settings are shown highlighted. Bit 3 to 0 Symbol SET_ICHP_PD2[3:0] Access Value Description R/W 01h integrating charge pump pd ( 45 deg. < error < 90 deg.)
Table 53. Bit 3 to 0
SET_ICHP_PFD register (address 12h) bit description Access Value Description R/W integrating charge pump pfd ( linear PLL)
Symbol SET_ICHP_PFD[3:0]
Table 54. Bit 3 to 0
SET_RATIO_PD1 register (address 13h) bit description Access Value Description R/W proportional charge pump pd ( error < 45 deg.)
Symbol SET_RATIO_PD1[3:0]
Table 55. SET_RATIO_PD2 (address 14h) bit description Default settings are shown highlighted. Bit Symbol Access Value R/W Description proportional charge pump pd ( 45 deg. < error < 90 deg.) 3 to 0 SET_RATIO_PD2[3:0]
DAC1408D650_1
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Objective data sheet
Rev. 01 -- 26 May 2009
46 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
SET_RATIO_PFD register (address 15h) bit description Access Value R/W Description proportional chargepump pfd ( linear PLL)
Table 56. Bit 7 to 0
Symbol SET_RATIO_PFD[3:0]
Table 57. SET_VCM_VOLTAGE register (address 16h) bit description Default settings are shown highlighted. Bit 7 Symbol SET_VCM[2:0] Access Value R/W Description set Vcm voltage levelr
Table 58. SET_SYNC register (address 17h) bit description Default settings are shown highlighted. Bit 7 to 4 1 to 0 Table 59. Bit 7 Symbol SET_SYNC_VCOM[3:0] SET_SYNC_LEVEL[3:0] Access Value R/W R/W Description set sync transmitter common mode level set sync transmitter outputlevel swing
MISC_CNTRLS register (address 1Ah) bit description Symbol SPI_DAC_MXSEL Access Value R/W 0 1 normal mode (inv_sinc a dac-inputs) io-bus direct mapped to dac-inputs ~sync = i_sync (normal operation) ~sync = f10_ln0 no action ring_oscillator test enabled deserializer test mode dac-tes mode ifdacdsp-mode (see section 3.2.1) cdi-mode (see section 3.2.1) soft reset cdi Description
6
TEST_CLK_FB
R/W 0 1
5
RING_OSC_TEST
R/W 0 1
4 3 2 1 0
DES_TEST DAC_TEST JD_MODE CDI_MODE SR_CDI
R/W R/W R/W R/W R/W
-
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
47 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 60. IO_MUX_CNTRL0 register (address 1Bh) bit description Default settings are shown highlighted. Bit 6 to 4 Symbol DSP-SEL[2:0] Access Value R/W 000 001 010 011 100 101 MX_DCLK <= EN_DATA_I_CDI and DATA_I_CDI_0 MX_DCLK <= EN_DATA_I_CDI and DATA_I_CDI_1OFF MX_DCLK <= EN_DATA_Q_CDI and DATA_Q_CDI_0 MX_DCLK <= EN_DATA_Q_CDI and DATA_Q_CDI_1 MX_DCLK <= I_EN and I_OUT(INVSINC_I_OUT) and "00" MX_DCLK <= Q_EN and Q_OUT(INVSINC_Q_OUT) and "00" others: MX_DCLK <= "101010101010101" MX_FCLK <= EN_DATA_I_DLP and DATA_I_DLP MX_FCLK <= EN_DATA_Q_DLP and DATA_Q_DLP MX_FCLK <= MON_DBG_BUS MX_FCLK <= "010101010101010" MX_A/MX_F10 <= DATA_LN0 / F10_LN0 MX_A/MX_F10 <= DATA_LN1 / F10_LN1 MX_A/MX_F10 <= DATA_LN2 / F10_LN2 MX_A/MX_F10 <= DATA_LN3 / F10_LN3 Description
3 to 2
DLP_SEL[1:0]
R/W 00 01 10 11
1 to 0
LN_SEL[1:0]
R/W 00 01 10 11
Table 61. Bit 4
IO_MUX_CNTRL1 register (address 1Ch) bit description Symbol SEL_RI Access Value R/W 0 1 RO_INTR <= INTR RO_INTR <= RINGOSCILLATOR MX_D <= MX_FCLK MX_D <= MX_DCLK IO[14:0] <= "00000" & MX_A IO[14:0] <= MX_D IO[15 ] <= RO_INTR IO[15] <= MX_F10 IO[15] <= FCLK IO[15] <= DCLK
(c) NXP B.V. 2009. All rights reserved.
Description
3
SEL_FD
R/W 0 1
2
SEL_AD
R/W 0 1
1 to 0
SEL_CK[1:0]
R/W 00 01 10 11
DAC1408D650_1
Objective data sheet
Rev. 01 -- 26 May 2009
48 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
DIG_VERSION register (address 1Dh) bit description Access Value R/W Description metalfixable version -id within digital (standard cell)
Table 62. Bit 7 to 0
Symbol DIG_VERSION_ID[7:0]
Table 63. Bit 7 to 0
JRX_ANA_VERSION register (address 1Eh) bit description Access Value Description metalfixable version -id within analog deserializer
Symbol
JRX_ANA_VERSION_ID[7:0] R/W
Table 64. Bit 2 to 0
PAGE_ADDRESS register (address 1Fh) bit description Access Value R/W Description page address
Symbol PAGE
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
49 of 88
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 10.15.2.5 Page 4 allocation map description
Table 65. Page 4 register allocation map R/W Bit definition b7 0 1 2 3 4 5 00h SR_DLP_0 01h SR_DLP_1 02h FORCE_LOCK 03h MAN_LOCK_ LN_1_0 05h CA_CNTRL 06h SCR-CNTRL 07h ILA_CNTRL 08h FORCE_ALIGN 09h MAN_ALIGN_ LN_0_1 R/W SR_SWA_ LN3 b6 SR_SWA_ LN2 b5 SR_SWA_ LN1 b4 b3 b2 b1 b0 Default Bin Hex SR_SWA_ SR_CA_LN3 SR_CA_LN2 SR_CA_LN1 SR_CA_LN0 00000000 00h LN0
Objective data sheet Rev. 01 -- 26 May 2009 50 of 88
DAC1408D650_1 (c) NXP B.V. 2009. All rights reserved.
NXP Semiconductors
Address Register name
R/W SR_CNTRL SR_CNTRL SR_CNTRL_ SR_CNTRL_ SR_DEC_LN SR_DEC_LN SR_DEC_LN SR_DEC_LN 00000000 00h _LN3 _LN2 LN1 LN0 3 2 1 0 R/W R/W FORCE_ FORCE_ FORCE_ LOCK_LN3 LOCK_LN2 LOCK_LN1 MAN_LOCK_LN1[3:0] MAN_LOCK_LN3[3:0] FORCE_ LOCK_LN0 SR_ILA 00000000 00h 00000000 00h 00000000 00h
MAN_LOCK_LN0[3:0] MAN_LOCK_LN2[3:0]
04h MAN_LOCK_2_0 R/W R/W
WORD_ WORD_ WORD_ WORD_ SELECT_RF SELECT_RF SELECT_RF SELECT_RF 00000000 00h SWAP_LN3 SWAP_LN2 SWAP_LN1 SWAP_LN0 _F10_LN3 _F10_LN2 _F10_LN1 _F10_LN0 FORCE_ SRC_LN3 FORCE_ SRC_LN2 FORCE_ SRC_LN1 SUP_LANE_ SYN FORCE_ 00000000 00h SRC_LN0 EN_SCR 10000011 83h
6 7 8 9
R/W MAN_SCR MAN_SCR_ MAN_SCR_ MAN_SCR_ _LN3 LN2 LN1 LN0 R/W R/W R/W R/W SEL_421_ 211 SEL_ILA[1:0] -
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
SEL_LOCK[2:0] -
DYN_ALIGN FORCE_ALI 00000000 00h _ENA GN 00000000 00h 00000000 00h 00000000 00h 00000000 00h POL_LN0 00000000 00h 11100100 E4h
MAN_ALIGN_LN1[3:0] MAN_ALIGN_LN3[3:0]
MAN_ALIGN_LN0[3:0] MAN_ALIGN_LN2[3:0] SEL_NIT_ERR_LN23 SEL_NIT_ERR_LN10
10 0Ah MAN_ALIGN_ LN_1_2 11 0Bh FA_ERR_ HANDLING 12 0Ch SYNCOUT_ MODE 13 0Dh LANE_ POLARITY 14 OEh LANE_SELECT 16 10h SOFT_RESET_ SCRAMBLER
R/W SEL_KOUT_UNEXP_LN SEL_KOUT_UNEXP_LN1 23 0 R/W R/W R/W R/W SEL_RE_INIT[2:0] SYNC_POL -
DAC1408D650
SEL_SYNC[3:0] POL_LN3 POL_LN2 POL_LN1
LANE_SEL_LN3[1:0] -
LANE_SEL_LN2[1:0] -
LANE_SEL_LN1[1:0]
LANE_SEL_LN0[1:0]
SR_SCR_LN SR_SCR_LN SR_SCR_LN SR_SCR_LN 00000000 00h 3 2 1 0 00000000 00h
17 11h INIT_SCR_S15T8 R/W _LN0
INIT_VALUE_S15_S8_LN0[7:0]
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 65. Page 4 register allocation map ...continued R/W Bit definition b7 18 12h INIT_SCR_ S7T1_LN0 19 13h INIT_SCR_ S15T8_LN1 20 14h INIT_SCR_ S7T1_LN1 21 15h INIT_SCR_ S15T8_LN2 22 16h INIT_SCR_ S7T1_LN2 23 17h INIT_SCR_ S15T8_LN3 24 18h INIT_SCR_ S7T1_LN3 25 19h INIT_ILA_ BUFPTR_LN01 26 1Ah INIT_ILA_ BUFPTR_LN23 27 1Bh ERROR_ HANDLING
Rev. 01 -- 26 May 2009
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet 51 of 88
DAC1408D650_1
NXP Semiconductors
Address Register name
Default b5 b4 b3 b2 b1 b0 Bin Hex INIT_VALUE_S7_S1_LN0[6:0] INIT_VALUE_S15_S8_LN1[7:0] 00000000 00h 00000000 00h 00000000 00h 00000000 00h 00000000 00h 00000000 00h 00000000 00h 10001000 88h 10001000 88h IGNORE_ 00000000 00h ERR 00000000 00h
b6 -
R/W R/W R/W R/W R/W R/W R/W R/W
-
INIT_VALUE_S7_S1_LN1[6:0] INIT_VALUE_S15_S8_LN2[7:0]
-
INIT_VALUE_S7_S1_LN2[6:0] INIT_VALUE_S15_S8_LN3[7:0]
INIT_ILA_BUFPTR_LN1[3:0]
INIT_VALUE_S7_S1_LN3[6:0] INIT_ILA_BUFPTR_LN0[3:0] INIT_ILA_BUFPTR_LN2[3:0] IMPL_ALT
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
R/W INIT_ILA_BUFPTR_LN3[3:0] R/W -
NAD_ERR_ KUX_CORR NAD_CORR CORR_MODE[1:0] CORR
29 1Fh PAGE_ADDRESS R/W PAGE
DAC1408D650
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
10.15.2.6
Page 4 bit definition detailed description Please refer to Table 65 for a register overview and their default values. In the following tables, all the values emphasized in bold are the default values.
Table 66. SR_DLP_0 register (address 00h) bit description Default settings are shown highlighted. Bit 7 6 5 4 3 2 1 0 Symbol SR_SWA_LN3 SR_SWA_LN2 SR_SWA_LN1 SR_SWA_LN0 SR_CA_LN3 SR_CA_LN2 SR_CA_LN1 SR_CA_LN0 Access Value Description R/W R/W R/W R/W R/W R/W R/W R/W 1 0 1 softreset sync_word_alignment lane_3 softreset sync_word_alignment lane_2 softreset sync_word_alignment lane_1 softreset sync_word_alignment lane_0 softreset clock_alignment lane_3 softreset clock_alignment lane_2 softreset clock_alignment lane_1 softreset clock_alignment lane_0
Table 67. SR_DLP_1 register (address 01h) bit description Default settings are shown highlighted. Bit 7 6 5 4 3 2 1 0 Symbol SR_CNTRL_LN3 SR_CNTRL_LN2 SR_CNTRL_LN1 SR_CNTRL_LN0 SR_DEC_LN3 SR_DEC_LN2 SR_DEC_LN1 SR_DEC_LN0 Access Value Description R/W R/W R/W R/W R/W R/W R/W R/W soft reset controller lane_3 soft reset controller lane_2 soft reset controller lane_1 soft reset controller lane_0 soft reset decoder_10b8b lane_3 soft reset decoder_10b8b lane_2 soft reset decoder_10b8b lane_1 soft reset decoder_10b8b lane_0
Table 68. FORCE_LOCK register (address 02h) bit description Default settings are shown highlighted. Bit Symbol 7 FORCE_LOCK_LN3 Access Value Description R/W 0 1 6 FORCE_LOCK_LN22 R/W 0 1 5 FORCE_LOCK_LN1 R/W 0 1 4 FORCE_LOCK_LN0 R/W 0 1 0 SR_ILA R/W automatic lock sync_word_alignment lane_0 manual lock sync_word_alignment lane_0 soft reset inter-lane-alignment automatic lock sync_word_alignment lane_1 manual lock sync_word_alignment lane_1 automatic lock sync_word_alignment lane_2 manual lock sync_word_alignment lane_2 automatic lock sync_word_alignment lane_3 manual lock sync_word_alignment lane_3
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
52 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 69. MAN_LOCK_LN_1_0 register (address 03h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description manual lock-settting sync-word-alignment lane_1 manual lock-settting sync-word-alignment lane_0 7 to 4 MAN_LOCK_LN1[3:0] R/W 3 to 0 MAN_LOCK_LN0[3:0] R/W Table 70. Bit 7 to 4 3 to 0
MAN_LOCK_2_0 register (address 04h) bit description Access Value Description manual lock-settting sync-word-alignment lane_3 manual lock-settting sync-word-alignment lane_2
Symbol
MAN_LOCK_LN3[3:0] R/W MAN_LOCK_LN2[3:0] R/W
Table 71. Bit 7
CA_CNTRL register (address 05h) bit description Access Value R/W 0 1 dout_ca_ln3[7:0] = din_ca_ln3[7:0] dout_ca_ln3[7:0] = din_ca_ln3[0:7] dout_ca_ln2[7:0] = din_ca_ln2[7:0] dout_ca_ln2[7:0] = din_ca_ln2[0:7] dout_ca_ln1[7:0] = din_ca_ln1[7:0] dout_ca_ln1[7:0] = din_ca_ln1[0:7] dout_ca_ln0[7:0] = din_ca_ln0[7:0] dout_ca_ln0[7:0] = din_ca_ln0[0:7] din_ca_ln3 sampled @ falling edge f10_ln3 din_ca_ln3 sampled @ rising edge f10_ln3 din_ca_ln2 sampled @ falling edge f10_ln2 din_ca_ln2 sampled @ rising edge f10_ln2 din_ca_ln1 sampled @ falling edge f10_ln1 din_ca_ln1 sampled @ rising edge f10_ln1 din_ca_ln0 sampled @ falling edge f10_ln0 din_ca_ln0 sampled @ rising edge f10_ln0 Description
Symbol WORD_SWAP_LN3
6
WORD_SWAP_LN2
R/W 0 1
5
WORD_SWAP_LN1
R/W 0 1
4
WORD_SWAP_LN0
R/W 0 1
3
SELECT_RF_F10_LN3
R/W 0 1
2
SELECT_RF_F10_LN2
R/W 0 1
0
SELECT_RF_F10_LN1
R/W 0 1
1
SELECT_RF_F10_LN0
R/W 0 1
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
53 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
SCR-CNTRL register (address 06h) bit description Access Value R/W 0 1 scrambling ln3 off (when force_scr_ln3 = 1) scrambling ln3 on (when force_scr_ln3 = 1) scrambling ln2 off (when force_scr_ln2 = 1) scrambling ln2 on (when force_scr_ln2 = 1) scrambling ln1 off (when force_scr_ln1 = 1) scrambling ln1 on (when force_scr_ln1 = 1) scrambling ln0 off (when force_scr_ln0 = 1) scrambling ln0 on (when force_scr_ln0 = 1) scrambling ln3 depends on lock_ln3 and en_scr scrambling ln3 depends on man_scr_ln3 scrambling ln2 depends on lock_ln2 and en_scr scrambling ln2 depends on man_scr_ln2 scrambling ln1 depends on lock_ln1 and en_scr scrambling ln1 depends on man_scr_ln1 scrambling ln0 depends on lock_ln0 and en_scr scrambling ln0 depends on man_scr_ln0 Description
Table 72. 7
Bit Symbol MAN_SCR_LN3
6
MAN_SCR_LN2
R/W 0 1
5
MAN_SCR_LN1
R/W 0 1
4
MAN_SCR_LN0
R/W 0 1
3
FORCE_SRC_LN3 R/W 0 1
2
FORCE_SRC_LN2 R/W 0 1
1
FORCE_SRC_LN1 R/W 0 1
0
FORCE_SRC_LN0 R/W 0 1
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
54 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
ILA_CNTRL register (address 07h) bit description Access Value R/W 0 1 inter-lane alignment based on ln3:ln2 and/or ln1:ln0 inter-lane alignment based on ln3:ln0 ila is done after receiving 1 /A/-symbol ila is done after receiving 2 /A/-symbols ila is done after receiving 3 /A/-symbols ila is done after receiving 4 /A/-symbols ila may start only if all (4 or 2) lanes are locked ila may start if one of the (4 or 2) lanes are locked ila may start if lane_0 is locked ila may start if lane_1 is locked ila may start if lane_2 is locked ila may start if lane_3 is locked inter lane alignment synchronization disabled inter lane alignment synchronization enabled data descrambling disabled scrambling ln0 depends on data descrambling enabled Description
Table 73. Bit 7
Symbol SEL_421_211
6 to 5 SEL_ILA[1:0]
R/W 00 01 10 11
4 to 2 SEL_LOCK[2:0]
R/W 000 001 010 011 100 101
1
SUP_LANE_SYN
R/W 0 1
0
EN_SCR
R/W 0 1
Table 74. 1
FORCE_ALIGN register (address 08h) bit description Access Value Description R/W 20h 0 1 no dynamic re-alignment dynamic re-alignment (and monitoring) enabled automatic lane alignment based on /A/-symbols manual lane alignment based on man_align_lnx
Bit Symbol DYN_ALIGN_ENA
0
FORCE_ALIGN
R/W
20h 0 1
Table 75. Bit
MAN_ALIGN_LN_0_1 register (address 09h) bit description Access Value Description 32h 32h indicates alignment data-delay for lane_1 [ 1..15] indicates alignment data-delay for lane_0 [ 1..15]
Symbol
7 to 4 MAN_ALIGN_LN1[3:0] R/W 3 to 0 MAN_ALIGN_LN0[3:0] R/W Table 76. Bit
MAN_ALIGN_LN_0_1 register (address 0Ah) bit description Access Value Description 32h 32h indicates alignment data-delay for lane_3 [ 1..15] indicates alignment data-delay for lane_2 [ 1..15]
(c) NXP B.V. 2009. All rights reserved.
Symbol
7 to 4 MAN_ALIGN_LN3[3:0] R/W 3 to 0 MAN_ALIGN_LN2[3:0] R/W
DAC1408D650_1
Objective data sheet
Rev. 01 -- 26 May 2009
55 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 77. FA_ERR_HANDLING register (address 0Bh) bit description Default settings are shown highlighted. Bit Symbol Access Value Description R/W 00 01 10 11 5 to 4 SEL_KOUT_ UNEXP_LN10[1:0] R/W 00 01 10 11 3 to 2 SEL_NIT_ERR_ LN23[1:0] R/W 00 01 10 11 1 to 0 SEL_NIT_ERR_ LN10[1:0] R/W 00 01 10 11 error_handling i.c.o. nit-errors in lane 0 or 1 error_handling i.c.o. nit-errors lane 0 and 1 error_handling i.c.o. nit-errors in lane 0 error_handling i.c.o. nit-errors in lane 1 error_handling i.c.o. nit-errors in lane 2 or 3 error_handling i.c.o. nit-errors lane 2 and 3 error_handling i.c.o. nit-errors in lane 2 error_handling i.c.o. nit-errors in lane 3 error_handling i.c.o. unexpected /K/ in lane 0 or 1 error_handling i.c.o. unexpected /K/ in lane 0 and 1 error_handling i.c.o. unexpected /K/ in lane 0 error_handling i.c.o. unexpected /K/ in lane 1 error_handling i.c.o. unexpected /K/ in lane 2 or 3 error_handling i.c.o. unexpected /K/ in lane 2 and 3 error_handling i.c.o. unexpected /K/ in lane 2 error_handling i.c.o. unexpected /K/ in lane 3 7 to 6 SEL_KOUT_ UNEXP_LN23[1:0]
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
56 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 78. SYNCOUT_MODE register (address 0Ch) bit description Default settings are shown highlighted. Bit 7 to 5 Symbol Access Value Description 000 001 010 011 100 101 110 111 4 SYNC_POL R/W 0 0 3 to 0 SEL_SYNC[3:0] R/W 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 other Table 79. Bit 3 sync when 1 of the 4 lane_sync's is active sync when all 4 lane_sync;s are active sync when sync_ln0 or sync_ln1 is active sync when both sync_ln0 and sync_ln1 are active sync when sync_ln2 or sync_ln3 is active sync when both sync_ln2 and sync_ln3 are active sync when sync_ln0 is active sync when sync_ln1 is active sync when sync_ln2 is active sync when sync_ln3 is active sync remains fixed '1' sync remains fixed '0' sync_out is active when low sync_out is active when high i_re_init when 1 of the lane_rst's is active i_re_init when rst_ln0 or rst_ln1 is active i_re_init when rst_ln2 or rst_ln3 is active i_re_init when rst_ln0 is active i_re_init when rst_ln1 is active i_re_init when rst_ln2 is active i_re_init when rst_ln3 is active i_re_init remains '0' SEL_RE_INIT[2:0] R/W
LANE_POLARITY register (address 1Dh) bit description Symbol POL_LN3L Access Value R/W 0 1 no action invert all databits of dout_ca_ln3[7:0] no action invert all databits of dout_ca_ln2[7:0] no action invert all databits of dout_ca_ln1[7:0] no action invert all databits of dout_ca_ln0[7:0] Description
2
POL_LN2
R/W 0 1
1
POL_LN1
R/W 0 1
0
POL_LN0
R/W
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
57 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 80. LANE_SELECT register (address 0Eh) bit description Default settings are shown highlighted. Bit 7 to 6 Symbol LANE_SEL_LN3[1:0] Access Value Description R/W 00 01 10 11 5 to 4 LANE_SEL_LN2[1:0] R/W 00 01 10 11 3 to 2 LANE_SEL_LN1[1:0] R/W 00 01 10 11 1 to 0 LANE_SEL_LN0[1:0] R/W 00 01 10 11 Table 81. Bit 3 ila_in_ln0 = lane_ln0 (dout and controls) ila_in_ln0 = lane_ln1 (dout and controls) ila_in_ln0 = lane_ln2 (dout and controls) ila_in_ln0 = lane_ln3 (dout and controls) ila_in_ln1 = lane_ln0 (dout and controls) ila_in_ln1 = lane_ln1 (dout and controls) ila_in_ln1 = lane_ln2 (dout and controls) ila_in_ln1 = lane_ln3 (dout and controls ila_in_ln2 = lane_ln0 (dout and controls) ila_in_ln2 = lane_ln1 (dout and controls) ila_in_ln2 = lane_ln2 (dout and controls) ila_in_ln2 = lane_ln3 (dout and controls) ila_in_ln3 = lane_ln0 (dout and controls) ila_in_ln3 = lane_ln1 (dout and controls) ila_in_ln3 = lane_ln2 (dout and controls) ila_in_ln3 = lane_ln3 (dout and controls)
SOFT_RESET_SCRAMBLER register (address 10h) bit description Symbol SR_SCR_LN3 Access Value R/W 0 1 no action soft_reset scrambler of lane0 no action soft_reset scrambler of lane1 no action soft_reset scrambler of lane2 no action soft_reset scrambler of lane3 Description
2
SR_SCR_LN2
R/W 0 1
1
SR_SCR_LN1
R/W 0 1
0
SR_SCR_LN0
R/W
Table 82. Bit
INIT_SCR_S15T8_LN0 register (address 11h) bit description Access Value Description init value for ln0 descrambler bits s15:s8
Symbol
7 to 0 INIT_VALUE_S15_S8_LN0[7:0] R/W
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
58 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
INIT_SCR_S7T1_LN0 (address 12h) bit description Access Value Description init value for ln0 descrambler bits s7:s1
Table 83. Bit
Symbol
6 to 0 INIT_VALUE_S7_S1_LN0[6:0] R/W
Table 84. INIT_SCR_S15T8_LN1 register (address 13h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 01h init value for ln1 descrambler bits s15:s8 7 to 0 INIT_VALUE_S15_S8_LN1[7:0] R/W Table 85. Bit 6 to 0
INIT_SCR_S7T1_LN1 register (address 14h) bit description Access Value Description R/W init value for ln1 descrambler bits s7:s1
Symbol INIT_VALUE_S7_S1_LN1[6:0]
Table 86. Bit 7 to 0
INIT_SCR_S15T8_LN2 register (address 15h) bit description Access Value Description init value for ln2 descrambler bits s15:s8
Symbol
INIT_VALUE_S15_S8_LN2[7:0] R/W
Table 87. INIT_SCR_S7T1_LN2 register (address 16h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description init value for ln2 descrambler bits s7:s1 6 to 0 INIT_VALUE_S7_S1_LN2[6:0] R/W Table 88. Bit
INIT_SCR_S15T8_LN3 register (address 17h) bit description Access Value Description init value for ln3 descrambler bits s15:s8
Symbol
7 to 0 INIT_VALUE_S15_S8_LN3[7:0] R/W
Table 89. INIT_SCR_S7T1_LN3 register (address 18h) bit description Default settings are shown highlighted. Bit Symbol 7 Access Value Description init value for ln3 descrambler bits s7:s1 INIT_VALUE_S7_S1_LN3[6:0] R/W
Table 90. INIT_ILA_BUFPTR_LN01 register (address 19h) bit description Default settings are shown highlighted. Bit 7 to 4 3 to 0 Symbol INIT_ILA_BUFPTR_LN1[3:0] INIT_ILA_BUFPTR_LN0[3:0] Access Value R/W R/W Description init value for ila bufptr ln1 init value for ila bufptr ln0
Table 91. INIT_ILA_BUFPTR_LN23 register (address 1Ah) bit description Default settings are shown highlighted. Bit 7 to 4 3 to 0 Symbol INIT_ILA_BUFPTR_LN3[3:0] INIT_ILA_BUFPTR_LN2[3:0] Access Value R/W R/W Description init value for ila bufptr ln3 init value for ila bufptr ln2
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
59 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 92. ERROR_HANDLING register (address 1Bh) bit description Default settings are shown highlighted. Bit 6 Symbol NAD_ERR_CORR Access Value R/W 0 1 5 KUX_CORR R/W 0 01 4 NAD_CORR R/W 0 1 3 to 2 CORR_MODE[1:0] R/W 00 01 10 11 1 IMPL_ALT R/W 0 01 0 IGNORE_ERR R/W 0 1 Table 93. Bit 2 to 0 no action ignore disparity/nit-errors @ lane-controller default disparity error detection (table-mode) alternative disparity error detection (cnt-mode) conceal 1 period @ fa conceal 2 periods @ fa conceal 3 periods @ fa conceal 4 periods @ fa nad-errors ignored (@fa) nad-errors concealment (@fa) unexpected k-character errors ignored (@fa) unexpected k-character errors concealment(2fa) nit-errors passed to frame-assembler (fa`) nad(nit- and disparity)-errors passed to fa Description
PAGE_ADDRESS register (address 1Fh) bit description Access Value R/W Description page_address
Symbol PAGE
DAC1408D650_1
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Objective data sheet
Rev. 01 -- 26 May 2009
60 of 88
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Table 94. Page 5 register allocation map R/W Bit definition b7 0 1 2 3 4 00h ILA_MON_1_0 01h ILA_MON_3_2 02h ILA_BUF_ERR 03h CA_MON 04h DEC_FLAGS R R R R R b6 b5 ILA_MON_LN1[3:0] ILA_MON_LN3[3:0] b4 b3 b2 b1 ILA_MON_LN0[3:0 ILA_MON_LN2[3:0] b0 Default Bin Hex
Objective data sheet Rev. 01 -- 26 May 2009 61 of 88
DAC1408D650_1 (c) NXP B.V. 2009. All rights reserved.
NXP Semiconductors
Address Register name
ILA_BUF_ER ILA_BUF_ER ILA_BUF_ER ILA_BUF_ER R_LN3 R_LN2 R_LN1 R_LN0 CA_MON_LN1[1:0] CA_MON_LN0[1:0]
CA_MON_LN3[1:0]
CA_MON_LN2[1:0]
DEC_NIT DEC_NIT DEC_NIT_E DEC_NIT_E DEC_DISP_ DEC_DISP_ DEC_DISP_ DEC_DISP_ _ERR_LN _ERR_LN RR_LN1 RR_LN0 ERR_LN3 ERR_LN2 ERR_LN1 ERR_LN0 3 2 K28_7_LN0 K28_7_LN1 K28_7_LN2 K28_7_LN3 DEC_KOUT_ DEC_KOUT_ DEC_KOUT_ DEC_KOUT_ LN3 LN2 LN1 LN0 K28_5_LN0 K28_5_LN1 K28_5_LN2 K28_5_LN3 K28_4_LN0 K28_4_LN1 K28_4_LN2 K28_4_LN3 K28_3_LN0 K28_3_LN1 K28_3_LN2 K28_3_LN3 K28_0_LN0 K28_0_LN1 K28_0_LN2 K28_0_LN3
5 6 6 7 8 9
05h KOUT_FLAG 06h K28_LN0_FLAG 07h K28_LN1_FLAG 08h K28_LN2_FLAG 09h K28_LN3_FLAG
R R R R R

Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating

0Ah KOUT_UNEXPEC R TED_FLAG
DEC_KOUT_ DEC_KOUT_ DEC_KOUT_ DEC_KOUT_ UNEXP_LN3 UNEXP_LN2 UNEXP_LN1 UNEXP_LN0 LOCK_CNT_MON_LN0[3:0] LOCK_CNT_MON_LN2[3:0] FLAG_CNT_LN0[7:0]
10 0Bh LOCK_CNT_MON R _LN01 11 0Ch LOCK_CNT_MON R _LN23 16 10h FLAG_CNT_LSB_ R LN0 17 11h FLAG_CNT_MSB_ R LN0 18 12h FLAG_CNT_LSB_ R LN1 19 13h FLAG_CNT_MSB_ R LN1 20 14h FLAG_CNT_LSB_ R LN2 21 15h FLAG_CNT_MSB_ R LN2
LOCK_CNT_MON_LN1[3:0] LOCK_CNT_MON_LN3[3:0]
DAC1408D650
FLAG_CNT_LN0[15:8] FLAG_CNT_LN1[7:0] FLAG_CNT_LN1[15:8] FLAG_CNT_LN2[7:0] FLAG_CNT_LN2[15:8]
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Table 94. Page 5 register allocation map ...continued R/W Bit definition b7 22 16h FLAG_CNT_LSB_ R LN3 23 17h FLAG_CNT_MSB_ R LN3 25 19h BER_LEVEL 26 1Ah INTR_ENA R/W R/W b6 b5 b4 b3 b2 b1 b0 FLAG_CNT_LN3[7:0] FLAG_CNT_LN3[15:8] BER_LEVEL[7:0] Default Bin Hex
Objective data sheet Rev. 01 -- 26 May 2009
(c) NXP B.V. 2009. All rights reserved. DAC1408D650_1
NXP Semiconductors
Address Register name
INTR_EN INTR_EN INTR_ENA_ INTR_ENA_ INTR_ENA_ INTR_ENA_ INTR_ENA_ INTR_ENA_ A_NIT A_DISP KOUT KOUT_UNE K28_7 K28_5 K28_3 K28_0 XP RST_CF C_LN1 RST_CF C_LN3 SEL_CFC_LN1[2:0] SEL_CFC_LN3[2:0] RST_CFC_L N0 RST_CFC_L N2 SEL_CFC_LN0[2:0] SEL_CFC_LN2[2:0] RST_K28_L N2_FLAGS RST_K28_L RST_K28_L N1_FLAGS N0_FLAGS DBG_MODE PAGE
27 1Bh CNTRL_FLAGCNT R/W _LN01 28 1Ch CNTRL_FLAGCNT R/W _LN23 29 1Dh MON_FLAGS_RE R/W SET 30 1Eh DBG_CNTRL R/W

RST_NIT RST_DIS RST_KOUT RST_KOUT_ RST_K28_L _ERR-FL P_ERR_F _FLAGS UNEXPECT N3_FLAGS AGS LAGS ED_FLAGS BER_MO INTR_CL DE EAR INTR_MODE
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating

31 1Fh PAGE_ADDRESS R/W
DAC1408D650
62 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
10.15.2.8
Page 5 bit definition detailed description Please refer to Table 94 for a register overview and their default values. In the following tables, all the values emphasized in bold are the default values.
Table 95. ILA_MON_1_0 register (address 00h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description R/W R/W ila_buf_ln1 pointer ila_buf_ln0 pointer 7 to 4 ILA_MON_LN1[3:0] 3 to 0 ILA_MON_LN0[3:0]
Table 96. ILA_MON_3_2 register (address 01h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description R/W R/W ila_buf_ln3 pointer ila_buf_ln2 pointer 7 to 4 ILA_MON_LN3[3:0] 3 to 0 ILA_MON_LN2[3:0]
Table 97. ILA_BUF_ERR register (address 02h) bit description Default settings are shown highlighted. Bit 3 Symbol ILA_BUF_ERR_LN3 Access R/W 0 1 2 ILA_BUF_ERR_LN2 R/W 0 1 1 ILA_BUF_ERR_LN1 R/W 0 1 0 ILA_BUF_ERR_LN0 R/W 0 1 ila_buf_ln0 pointer is in range ila_buf_ln0 pointer is out of range ila_buf_ln1 pointer is in range ila_buf_ln1 pointer is out of range ila_buf_ln2 pointer is in range ila_buf_ln2 pointer is out of range ila_buf_ln3 pointer is in range ila_buf_ln3 pointer is out of range Value Description
Table 98. CA_MON register (address 03h) bit description Default settings are shown highlighted. Bit 7 to 6 5 to 4 3 to 2 1 to 0 Symbol CA_MON_LN3[1:0] CA_MON_LN2[1:0] CA_MON_LN1[1:0] CA_MON_LN0[1:0] Access R/W R/W R/W R/W Value Description clock alignment phase monitor lane_3 clock alignment phase monitor lane_2 clock alignment phase monitor lane_1 clock alignment phase monitor lane_0
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
63 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
DEC_FLAGS register (address 04h) bit description Access Value Description R/W R/W R/W R/W R/W R/W R/W R/W not-in-table-errorflag lane_3 not-in-table-errorflag lane_2 not-in-table-errorflag lane_1 not-in-table-errorflag lane_0 disparity-errorflag lane_3 disparity-errorflag lane_2 disparity-errorflag lane_1 disparity-errorflag lane_0
Table 99. Bit 7 6 5 4 3 2 1 0
Symbol DEC_NIT_ERR_LN3 DEC_NIT_ERR_LN2 DEC_NIT_ERR_LN1 DEC_NIT_ERR_LN0 DEC_DISP_ERR_LN3 DEC_DISP_ERR_LN2 DEC_DISP_ERR_LN1 DEC_DISP_ERR_LN0
Table 100. KOUT_FLAG register (address 05h) bit description Bit 3 2 1 0 Symbol DEC_KOUT_LN3 DEC_KOUT_LN2 DEC_KOUT_LN1 DEC_KOUT_LN0 Access Value Description R/W R/W R/W R/W /K/-symbols found in lane_3 /K/-symbols found in lane_2 /K/-symbols found in lane_1 /K/-symbols found in lane_0
Table 101. K28_LN0_FLAG register (address 06h) bit description Bit 4 3 2 1 0 Symbol K28_7_LN0 K28_5_LN0 K28_4_LN0 K28_3_LN0 K28_0_LN0 Access Value Description R/W R/W R/W R/W R/W k28_7 /F/ -symbols found in lane_0 k28_5 /K/ -symbols found in lane_0 k28_4 /Q/ -symbols found in lane_0 k28_3 /A/ -symbols found in lane_0 k28_0 /R/ -symbols found in lane_0
Table 102. K28_LN1_FLAG register (address 07h) bit description Bit 4 3 2 1 0 Symbol K28_7_LN1 K28_5_LN1 K28_4_LN1 K28_3_LN1 K28_0_LN1 Access Value Description R/W R/W R/W R/W R/W k28_7 /F/ -symbols found in lane_1 k28_5 /K/ -symbols found in lane_1 k28_4 /Q/ -symbols found in lane_1 k28_3 /A/ -symbols found in lane_1 k28_0 /R/ -symbols found in lane_1
Table 103. K28_LN2_FLAG register (address 08h) bit description Bit 4 3 2 1 0 Symbol K28_7_LN2 K28_5_LN2 K28_4_LN2 K28_3_LN2 K28_0_LN2 Access Value Description R/W R/W R/W R/W R/W k28_7 /F/ -symbols found in lane_2 k28_5 /K/ -symbols found in lane_2 k28_4 /Q/ -symbols found in lane_2 k28_3 /A/ -symbols found in lane_2 k28_0 /R/ -symbols found in lane_2
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
64 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 104. K28_LN3_FLAG register (address 09h) bit description Bit 4 3 2 1 0 Symbol K28_7_LN3 K28_5_LN3 K28_4_LN3 K28_3_LN3 K28_0_LN3 Access Value Description R/W R/W R/W R/W R/W k28_7 /F/ -symbols found in lane_3 k28_5 /K/ -symbols found in lane_3 k28_4 /Q/ -symbols found in lane_3 k28_3 /A/ -symbols found in lane_3 k28_0 /R/ -symbols found in lane_3
Table 105. LOCK_CNT_MON_LN01 register (address 0Ah) bit description Bit 3 2 1 0 Symbol DEC_KOUT_UNEXP_LN3 DEC_KOUT_UNEXP_LN2 DEC_KOUT_UNEXP_LN1 DEC_KOUT_UNEXP_LN0 Access Value Description R/W R/W R/W R/W Unexpected /K/-symbols found in lane_3 Unexpected /K/-symbols found in lane_2 Unexpected /K/-symbols found in lane_1 Unexpected /K/-symbols found in lane_0
Table 106. ILA_MON_3_2 register (address 0Bh) bit description Default settings are shown highlighted. Bit Symbol Access Value Description lock_state monitor sync-word-alignment ln1 lock_state monitor sync-word-alignment ln0 7 to 4 LOCK_CNT_MON_LN1[3:0] R/W 3 to 0 LOCK_CNT_MON_LN0[3:0] R/W
Table 107. LOCK_CNT_MON_LN23 register (address 0Ch) bit description Default settings are shown highlighted. Bit Symbol Access Value Description lock_state monitor sync-word-alignment ln3 lock_state monitor sync-word-alignment ln2 7 to 4 LOCK_CNT_MON_LN3[3:0] R/W 3 to 0 LOCK_CNT_MON_LN2[3:0] R/W
Table 108. FLAG_CNT_LSB_LN0 register (address 10h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description R/W lsb's of flag_counter ln0 7 to 0 IFLAG_CNT_LN0[7:0]
Table 109. FLAG_CNT_MSB_LN0 register (address 11h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description R/W msb's of flag_counter ln0 7 to 0 FLAG_CNT_LN0[15:8]
Table 110. FLAG_CNT_LSB_LN1 register (address 12h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description R/W lsb's of flag_counter ln1 7 to 0 FLAG_CNT_LN1[7:0]
Table 111. FLAG_CNT_MSB_LN1 register (address 13h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description R/W msb's of flag_counter ln11
(c) NXP B.V. 2009. All rights reserved.
7 to 0 FLAG_CNT_LN1[15:8]
DAC1408D650_1
Objective data sheet
Rev. 01 -- 26 May 2009
65 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 112. FLAG_CNT_LSB_LN2 register (address 14h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description R/W lsb's of flag_counter ln2 7 to 0 FLAG_CNT_LN2[7:0]
Table 113. FLAG_CNT_MSB_LN2 register (address 15h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description R/W msb's of flag_counter ln2 7 to 0 FLAG_CNT_LN2[15:8]
Table 114. FLAG_CNT_LSB_LN3 register (address 16h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description R/W lsb's of flag_counter ln3 7 to 0 FLAG_CNT_LN3[7:0]
Table 115. FLAG_CNT_MSB_LN3 register (address 17h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description R/W msb's of flag_counter ln3 7 to 0 FLAG_CNT_LN3[15:8]
Table 116. BER_LEVEL register (address 19h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description R/W level used for simple(dc) ber-measurement 7 to 0 BER_LEVEL[7:0]
Table 117. INTR_ENA register (address 1Ah) bit description Bit Symbol 7 INTR_ENA_NIT Access Value Description R/W 0 1 6 INTR_ENA_DISP R/W 0 1 5 INTR_ENA_KOUT R/W 0 1 4 INTR_ENA_KOUT_UNEXP R/W 0 1 3 INTR_ENA_K28_7 R/W 0 1 no action detection k28_7 in ln affects i_ln no action] detection unexpected kchar in ln affects i_ln no action detection k-controlcharacter in ln affects i_ln no action disparity-error in ln affects i_ln no action nit-error in ln affects i_ln
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
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NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 117. INTR_ENA register (address 1Ah) bit description ...continued Bit Symbol 2 INTR_ENA_K28_5 Access Value Description R/W 0 1 1 INTR_ENA_K28_3 R/W 0 1 0 INTR_ENA_K28_0 R/W 0 1 no action detection k28_0 in ln affects i_ln no action detection k28_3 in ln affects i_ln no action detection k28_5 in ln affects i_ln
Table 118. CNTRL_FLAGCNT_LN01 register (address 1Bh) bit description Default settings are shown highlighted. Bit 7 3 Symbol RST_CFC_LN1 RST_CFC_LN0 Access Value Description R/W R/W reset flagcnt ln1 select cnt-enable flagcnt ln1 (see section 4.4) reset flagcnt ln0 select cnt-enable flagcnt ln0 (see section 4.4)
6 to 4 SEL_CFC_LN1[2:0] R/W 2 to 0 SEL_CFC_LN0[2:0] R/W
Table 119. CNTRL_FLAGCNT_LN23 register (address 1Ch) bit description Default settings are shown highlighted. Bit 7 3 Symbol RST_CFC_LN3 RST_CFC_LN2 Access Value Description R/W R/W reset flagcnt ln3 select cnt-enable flagcnt ln3 (see section 4.4) reset flagcnt ln2 select cnt-enable flagcnt ln2 (see section 4.4)
6 to 4 SEL_CFC_LN3[2:0] R/W 2 to 0 SEL_CFC_LN2[2:0] R/W
Table 120. MON_FLAGS_RESET register (address 1Dh) bit description Bit 7 6 5 4 3 2 1 0 Symbol RST_NIT_ERR-FLAGS RST_DISP_ERR_FLAGS RST_KOUT_FLAGS RST_KOUT_UNEXPECTE D_FLAGS RST_K28_LN3_FLAGS RST_K28_LN2_FLAGS RST_K28_LN1_FLAGS RST_K28_LN0_FLAGS0 Access Value Description R/W R/W R/W R/W R/W R/W R/W R/W reset nit-error monitor flags reset disparity monitor flags reset k-symbols monitor flags reset unexpected k-symbols monitor flags reset k28_x monitor flags for ln3 reset k28_x monitor flags for ln2 reset k28_x monitor flags for ln1 reset k28_x monitor flags for ln0
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
67 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 121. DBG_CNTRL register (address 1Eh) bit description Bit 7 Symbol BER_MODE Access Value R/W 0 1 6 INTR_CLEAR R/W 00 01 5 to 3 INTR_MODE[2:0] R/W 000 001 010 011 100 101 110 111 2 to 0 DBG_MODE R/W intr depends on i_ln0 intr depends on i_ln1 intr depends on i_ln2 intr depends on i_ln3 intr depends on i_ln0 or i_ln1 intr depends on i_ln2 or i_ln3 intr depends on i_ln0 or i_ln1 or i_ln2 or i_ln3 no interrupt selects signals for mon_dbg_bus (see section A.1) no action clear interrupt (to '1')s no action simple BER-measurement enabled Description
Table 122. PAGE_ADDRESS register (address 1Fh) bit description Bit 2 to 0 Symbol PAGE Access Value R/W Description page_address
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
68 of 88
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Table 123. Page 6 register allocation map Address 0 1 2 3 4 5 6 7 8 9 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h Register name LN0_CFG_0 LN0_CFG_1 LN0_CFG_2 LN0_CFG_3 LN0_CFG_4 LN0_CFG_5 LN0_CFG_6 LN0_CFG_7 LN0_CFG_8 LN0_CFG_9 LN0_CFG_10 LN0_CFG_11 LN0_CFG_12 LN0_CFG_13 LN1_CFG_0 LN1_CFG_1 LN1_CFG_2 LN1_CFG_3 LN1_CFG_4 LN1_CFG_5 LN1_CFG_6 LN1_CFG_7 LN1_CFG_8 LN1_CFG_9 LN1_CFG_10 LN1_CFG_11 R/W Bit definition b7 R R R R R R R R R R R R R R R R R R R R R R R R R R LN1_CS[1:0] LN1_HD LN1_RES1[7:0] LN1_M[7:0] LN1_N[4:0] LN1_N'[4:0] LN1_S[4:0] LN1_CF[4:0] LN1_SCR LN1_F[7:0] LN1_K[4:0] LN0_CS[1:0] LN0_HD LN0_RES1[7:0] LN0_RES2[7:0] LN0_FCHK[7:0] LN1_DID[7:0] LN1_BID[3:0] LN1_LID[4:0] LN1_L[4:0] LN0_M[7:0] LN0_N[4:0] LN0_N'[4:0] LN0_S[4:0] LN0_CF[4:0] LN0_SCR LN0_F[7:0] LN0_K[4:0] b6 b5 b4 b3 LN0_DID[7:0] LN0_BID[3:0] LN0_LID[4:0] LN0_L[4:0] b2 b1 b0 Default Bin Hex
Objective data sheet Rev. 01 -- 26 May 2009 69 of 88
DAC1408D650_1 (c) NXP B.V. 2009. All rights reserved.
NXP Semiconductors
10 0Ah 11 0Bh 12 0Ch 13 0Dh 16 10h 17 11h 18 12h 19 13h 20 14h 21 15h 22 16h 23 17h 24 18h 25 19h 26 1Ah 27 1Bh
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating

DAC1408D650
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Table 123. Page 6 register allocation map ...continued Address 28 1Ch 29 1Dh 31 1Fh Register name LN1_CFG_12 LN1_CFG_13 R/W Bit definition b7 R R b6 b5 b4 b3 LN1_RES2[7:0] LN1_FCHK[7:0] PAGE b2 b1 b0 Default Bin Hex
Objective data sheet Rev. 01 -- 26 May 2009
(c) NXP B.V. 2009. All rights reserved. DAC1408D650_1
NXP Semiconductors
PAGE_ADDRESS R/W
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
DAC1408D650
70 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
10.15.2.10
Page 6 bit definition detailed description Please refer to Table 123 for a register overview and their default values. In the following tables, all the values emphasized in bold are the default values.
Table 124. LN0_CFG_0 register (address 00h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description R/W 7 to 0 LN0_DID[7:0]
Table 125. LN0_CFG_1 register (address 01h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description R/W 3 to 0 LN0_BID[3:0]
Table 126. LN0_CFG_2 register (address 02h) bit description Default settings are shown highlighted. Bit 4 to 0 Symbol LN0_LID[4:0] Access R/W Value Description
Table 127. LN0_CFG_3 register (address 03h) bit description Default settings are shown highlighted. Bit 7 4 to 0 Symbol LN0_SCR LN0_L[4:0] Access R/W R/W Value Description
Table 128. LN0_CFG_4 register (address 04h) bit description Bit 7 to 0 Symbol LN0_F[7:0] Access Value Description R/W
Table 129. LN0_CFG_5 register (address 05h) bit description Bit 4 to 0 Symbol LN0_K[4:0] Access Value R/W Description
Table 130. LN0_CFG_6 register (address 06h) bit description Bit 4 to 0 Symbol LN0_M[7:0] Access Value R/W Description
Table 131. LN0_CFG_7 register (address 07h) bit description Bit 7 to 6 4 to 0 Symbol LN0_CS[1:0] LN0_N[4:0] Access Value R/W R/W Description
Table 132. LN0_CFG_8 register (address 08h) bit description Bit 4 to 0 Symbol LN0_N'[4:0] Access Value R/W Description
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
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NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 133. LN0_CFG_9 register (address 09h) bit description Bit 4 to 0 Symbol LN0_S[4:0] Access Value R/W Description
Table 134. LN0_CFG_10 register (address 0Ah) bit description Bit 7 4 to 0 Symbol LN0_HD LN0_CF[4:0] Access Value R/W R/W Description
Table 135. LN0_CFG_11 register (address 0Bh) bit description Bit 7 to 0 Symbol LN0_RES1[7:0] Access Value R/W Description
Table 136. LN0_CFG_12 register (address 0Ch) bit description Bit 7 to 0 Symbol LN0_RES2[7:0] Access Value R/W Description
Table 137. LN0_CFG_13 register (address 0Dh) bit description Bit 7 to 0 Symbol LN0_FCHK[7:0] Access Value R/W Description
Table 138. LN1_CFG_0 register (address 10h) bit description Bit 7 to 0 Symbol LN1_DID[7:0] Access Value R/W Description
Table 139. LN1_CFG_1 register (address 11h) bit description Bit 3 to 0 Symbol LN1_BID[3:0] Access Value R/W Description
Table 140. LN1_CFG_2 register (address 12h) bit description Bit 4 to 0 Symbol LN1_LID[4:0] Access Value R/W Description
Table 141. LN1_CFG_3 register (address 13h) bit description Bit 7 4 to 0 Symbol LN1_SCR LN1_L[4:0] Access Value R/W R/W Description
Table 142. LN1_CFG_4 register (address 14h) bit description Bit 7 to 0 Symbol LN1_F[7:0] Access Value R/W Description
Table 143. LN1_CFG_5 register (address 15h) bit description Bit 4 to 0
DAC1408D650_1
Symbol LN1_K[4:0]
Access Value R/W
Description
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
72 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 144. LN1_CFG_6 register (address 16h) bit description Bit 4 to 0 Symbol LN1_M[7:0] Access Value R/W Description
Table 145. LN1_CFG_7 register (address 17h) bit description Bit 7 to 6 4 to 0 Symbol LN1_CS[1:0] LN1_N[4:0] Access Value R/W R/W Description
Table 146. LN1_CFG_8 register (address 18h) bit description Bit 4 to 0 Symbol LN1_N'[4:0] Access Value R/W Description
Table 147. LN1_CFG_9 register (address 19h) bit description Bit 4 to 0 Symbol LN1_S[4:0] Access Value R/W Description
Table 148. LN1_CFG_10 register (address 1Ah) bit description Bit 7 to 6 4 to 0 Symbol LN1_HD LN1_CF[4:0] Access Value R/W R/W Description
Table 149. LN1_CFG_11 register (address 1Bh) bit description Bit 7 to 0 Symbol LN1_RES1[7:0] Access Value R/W Description
Table 150. LN1_CFG_12 register (address 1Ch) bit description Bit 7 to 0 Symbol LN1_RES2[7:0] Access Value R/W Description
Table 151. LN1_CFG_13 register (address 1Dh) bit description Bit 7 to 0 Symbol LN1_FCHK[7:0] Access Value R/W Description
Table 152. PAGE_ADDRESS register (address 1Fh) bit description Bit 2 to 0 Symbol PAGE Access Value R/W Description page_address
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
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73 of 88
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 10.15.2.11 Page 7 allocation map description
Table 153. Page 7 register allocation map Address 0 1 2 3 4 5 6 7 8 9 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h Register name LN2_CFG_0 LN2_CFG_1 LN2_CFG_2 LN2_CFG_3 LN2_CFG_4 LN2_CFG_5 LN2_CFG_6 LN2_CFG_7 LN2_CFG_8 LN2_CFG_9 LN2_CFG_10 LN2_CFG_11 LN2_CFG_12 LN2_CFG_13 LN3_CFG_0 LN3_CFG_1 LN3_CFG_2 LN3_CFG_3 LN3_CFG_4 LN3_CFG_5 LN3_CFG_6 LN3_CFG_7 LN3_CFG_8 LN3_CFG_9 LN3_CFG_10 LN3_CFG_11 R/W Bit definition b7 R R R R R R R R R R R R R R R R R R R R R R R R R R LN3_CS[1:0] LN3_HD LN3_RES1[7:0] LN3_M[7:0] LN3_N[4:0] LN3_N'[4:0] LN3_S[4:0] LN3_CF[4:0] LN3_SCR LN3_F[7:0] LN3_K[4:0] LN2_CS[1:0] LN2_HD LN2_RES1[7:0] LN2_RES2[7:0] LN2_FCHK[7:0] LN3_DID[7:0] LN3_BID[3:0] LN3_LID[4:0] LN3_L[4:0] LN2_M[7:0] LN2_N[4:0] LN2_N'[4:0] LN2_S[4:0] LN2_CF[4:0] LN2_SCR LN2_F[7:0] LN2_K[4:0] b6 b5 b4 b3 LN2_DID[7:0] LN2_BID[3:0] LN2_LID[4:0] LN2_L[4:0] b2 b1 b0 Default Bin Hex
Objective data sheet Rev. 01 -- 26 May 2009 74 of 88
DAC1408D650_1 (c) NXP B.V. 2009. All rights reserved.
NXP Semiconductors
10 0Ah 11 0Bh 12 0Ch 13 0Dh 16 10h 17 11h 18 12h 19 13h 20 14h 21 15h 22 16h 23 17h 24 18h 25 19h 26 1Ah 27 1Bh
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating

DAC1408D650
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 153. Page 7 register allocation map ...continued Address 28 1Ch 29 1Dh 31 1Fh Register name LN3_CFG_12 LN3_CFG_13 R/W Bit definition b7 R R b6 b5 b4 b3 LN3_RES2[7:0] LN3_FCHK[7:0] PAGE b2 b1 b0 Default Bin Hex
Objective data sheet Rev. 01 -- 26 May 2009
(c) NXP B.V. 2009. All rights reserved. DAC1408D650_1
NXP Semiconductors
PAGE_ADDRESS R/W
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
DAC1408D650
75 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
10.15.2.12
Page 7 bit definition detailed description Please refer to Table 153 for a register overview and their default values. In the following tables, all the values emphasized in bold are the default values.
Table 154. LN2_CFG_0 register (address 00h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description R/W 7 to 0 LN2_DID[7:0]
Table 155. LN2_CFG_1 register (address 01h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description R/W 3 to 0 LN2_BID[3:0]
Table 156. LN2_CFG_2 register (address 02h) bit description Default settings are shown highlighted. Bit 4 to 0 Symbol LN2_LID[4:0] Access R/W Value Description
Table 157. LN2_CFG_3 register (address 03h) bit description Default settings are shown highlighted. Bit 7 4 to 0 Symbol LN2_SCR LN2_L[4:0] Access R/W R/W Value Description
Table 158. LN2_CFG_4 register (address 04h) bit description Bit 7 to 0 Symbol LN2_F[7:0] Access Value Description R/W
Table 159. LN2_CFG_5 register (address 05h) bit description Bit 4 to 0 Symbol LN2_K[4:0] Access Value R/W Description
Table 160. LN2_CFG_6 register (address 06h) bit description Bit 4 to 0 Symbol LN2_M[7:0] Access Value R/W Description
Table 161. LN2_CFG_7 register (address 07h) bit description Bit 7 to 6 4 to 0 Symbol LN2_CS[1:0] LN2_N[4:0] Access Value R/W R/W Description
Table 162. LN2_CFG_8 register (address 08h) bit description Bit 4 to 0 Symbol LN2_N'[4:0] Access Value R/W Description
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
76 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 163. LN2_CFG_9 register (address 09h) bit description Bit 4 to 0 Symbol LN2_S[4:0] Access Value R/W Description
Table 164. LN2_CFG_10 register (address 0Ah) bit description Bit 7 4 to 0 Symbol LN2_HD LN2_CF[4:0] Access Value R/W R/W Description
Table 165. LN2_CFG_11 register (address 0Bh) bit description Bit 7 to 0 Symbol LN2_RES1[7:0] Access Value R/W Description
Table 166. LN2_CFG_12 register (address 0Ch) bit description Bit 7 to 0 Symbol LN2_RES2[7:0] Access Value R/W Description
Table 167. LN2_CFG_13 register (address 0Dh) bit description Bit 7 to 0 Symbol LN2_FCHK[7:0] Access Value R/W Description
Table 168. LN3_CFG_0 register (address 10h) bit description Bit 7 to 0 Symbol LN3_DID[7:0] Access Value R/W Description
Table 169. LN3_CFG_1 register (address 11h) bit description Bit 3 to 0 Symbol LN3_BID[3:0] Access Value R/W Description
Table 170. LN3_CFG_2 register (address 12h) bit description Bit 4 to 0 Symbol LN3_LID[4:0] Access Value R/W Description
Table 171. LN3_CFG_3 register (address 13h) bit description Bit 7 4 to 0 Symbol LN3_SCR LN3_L[4:0] Access Value R/W R/W Description
Table 172. LN3_CFG_4 register (address 14h) bit description Bit 7 to 0 Symbol LN3_F[7:0] Access Value R/W Description
Table 173. LN3_CFG_5 register (address 15h) bit description Bit 4 to 0
DAC1408D650_1
Symbol LN3_K[4:0]
Access Value R/W
Description
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
77 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
Table 174. LN3_CFG_6 register (address 16h) bit description Bit 4 to 0 Symbol LN3_M[7:0] Access Value R/W Description
Table 175. LN3_CFG_7 register (address 17h) bit description Bit 7 to 6 4 to 0 Symbol LN3_CS[1:0] LN3_N[4:0] Access Value R/W R/W Description
Table 176. LN3_CFG_8 register (address 18h) bit description Bit 4 to 0 Symbol LN3_N'[4:0] Access Value R/W Description
Table 177. LN3_CFG_9 register (address 19h) bit description Bit 4 to 0 Symbol LN3_S[4:0] Access Value R/W Description
Table 178. LN3_CFG_10 register (address 1Ah) bit description Bit 7 4 to 0 Symbol LN3_HD LN3_CF[4:0] Access Value R/W R/W Description
Table 179. LN3_CFG_11 register (address 1Bh) bit description Bit 7 to 0 Symbol LN3_RES1[7:0] Access Value R/W Description
Table 180. LN3_CFG_12 register (address 1Ch) bit description Bit 7 to 0 Symbol LN3_RES2[7:0] Access Value R/W Description
Table 181. LN3_CFG_13 register (address 1Dh) bit description Bit 7 to 0 Symbol LN3_FCHK[7:0] Access Value R/W Description
Table 182. PAGE_ADDRESS register (address 1Fh) bit description Bit 2 to 0 Symbol PAGE Access Value R/W Description page_address
DAC1408D650_1
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Objective data sheet
Rev. 01 -- 26 May 2009
78 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
11. Package outline
HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad
SOT638-1
c y exposed die pad side X Dh 75 76 51 50 ZE
A
e E HE wM bp pin 1 index Lp L detail X
Eh
A
A2
A1
(A3)
100 1 wM ZD 25 bp D HD
26
e
vM A B vM B
0 scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D(1) 14.1 13.9 Dh 7.1 6.1 E(1) 14.1 13.9 Eh 7.1 6.1 e 0.5 HD
10 mm
HE
L 1
Lp 0.75 0.45
v 0.2
w 0.08
y 0.08
ZD(1) ZE(1) 1.15 0.85 1.15 0.85
7 0
16.15 16.15 15.85 15.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT638-1 REFERENCES IEC JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 03-04-07 05-02-02
Fig 22. Package outline SOT638 (HTQFP100)
DAC1408D650_1 (c) NXP B.V. 2009. All rights reserved.
Objective data sheet
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NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
12. Abbreviations
Table 183. Abbreviations Acronym BW BWA CDMA CML CMOS DAC EDGE FIR GSM IF IMD3 LMDS LVDS NCO NMOS PLL SERDES SFDR SPI WCDMA WLL Description Bandwidth Broadband Wireless Access Code Division Multiple Access Current Mode Logic Complementary Metal Oxide Semiconductor Digital-to-Analog Converter Enhanced Data rates for GSM Evolution Finite Impulse Response Global System for Mobile communications Intermediate Frequency Third Order Intermodulation Product Local Multipoint Distribution Service Low-voltage Differential Signaling Numerically Controlled Oscillator Negative Metal-Oxide Semiconductor Phase-Locked Loop Serializer/Deserializer Spurious Free Dynamic Range Serial Peripheral Interface Wideband Code Division Multiple Access Wireless Local Loop
DAC1408D650_1
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Objective data sheet
Rev. 01 -- 26 May 2009
80 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
13. Revision history
Table 184. Revision history Document ID DAC1408D650_1 Release date 20090526 Data sheet status Objective data sheet Change notice Supersedes -
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
81 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
14. Legal information
14.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
14.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
82 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
16. Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .8 Thermal characteristics . . . . . . . . . . . . . . . . . . .8 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .9 Digital Layer Processing Latency . . . . . . . . . . .15 SYNC_OUT timing . . . . . . . . . . . . . . . . . . . . . .17 Read or Write mode access description . . . . .21 Number of bytes to be transferred . . . . . . . . . .21 SPI timing characteristics . . . . . . . . . . . . . . . .22 Interpolation filter coefficients . . . . . . . . . . . . .24 Inversion filter coefficients . . . . . . . . . . . . . . . .26 DAC transfer function . . . . . . . . . . . . . . . . . . . .26 IO(fs) coarse adjustment . . . . . . . . . . . . . . . . . .28 IO(fs) fine adjustment . . . . . . . . . . . . . . . . . . . .28 Digital offset adjustment . . . . . . . . . . . . . . . . .29 Auxiliary DAC transfer function . . . . . . . . . . . .30 Page 0 register allocation map . . . . . . . . . . . .36 COMMON register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .37 TXCFG register (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .38 PLLCFG register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .39 FREQNCO_LSB register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .39 FREQNCO_LISB register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .39 FREQNCO_UISB register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .39 FREQNCO_MSB register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .39 PHINCO_LSB register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .39 PHINCO_MSB register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .40 DAC_A_CFG_1 register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .40 DAC_A_CFG_2 register (address 0Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . .40 DAC_A_CFG_3 register (address 0Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .40 DAC_B_CFG_1 register (address 0Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .40 DAC_B_CFG_2 register (address 0Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .40 DAC_B_CFG_3 register (address 0Eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .41 Table 34. DAC_CFG register (address 0Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 35. DAC_A_Aux_MSB register (address 1Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 36. DAC_A_Aux_LSB register (address 1Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 37. DAC_B_Aux_MSB register (address 1Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 38. DAC_B_Aux_LSB register (address 1Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 39. Page 2 register allocation map . . . . . . . . . . . . 42 Table 40. MAINCONTROL register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 41. MAN_PON register (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 42. MAN_SUPD register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 43. RST_EXT_FCLK register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 44. RST_EXT_DCLK register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 45. DCSMU_PREDIVCNT register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 46. PLL_CHARGETIME register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 47. PLL_RUN_IN_TIME register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 48. CA_RUN_IN_TIME register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 49. IQ_LEVEL_CNTRL register (address 0Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 50. IQ_DC_LEVEL_LSB register (address 0Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 51. SET_ICHP_PD1 register (address 10h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 52. SET_ICHP_PD2 register (address 11h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 53. SET_ICHP_PFD register (address 12h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 54. SET_RATIO_PD1 register (address 13h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 55. SET_RATIO_PD2 (address 14h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 56. SET_RATIO_PFD register (address 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 57. SET_VCM_VOLTAGE register (address 16h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 58. SET_SYNC register (address 17h)
continued >>
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
83 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
(address 13h) bit description . . . . . . . . . . . . . . 59 Table 85. INIT_SCR_S7T1_LN1 register (address 14h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 86. INIT_SCR_S15T8_LN2 register (address 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 87. INIT_SCR_S7T1_LN2 register (address 16h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 88. INIT_SCR_S15T8_LN3 register (address 17h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 89. INIT_SCR_S7T1_LN3 register (address 18h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 90. INIT_ILA_BUFPTR_LN01 register (address 19h) bit description . . . . . . . . . . . . . . 59 Table 91. INIT_ILA_BUFPTR_LN23 register (address 1Ah) bit description . . . . . . . . . . . . . 59 Table 92. ERROR_HANDLING register (address 1Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 93. PAGE_ADDRESS register (address 1Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 94. Page 5 register allocation map . . . . . . . . . . . . 61 Table 95. ILA_MON_1_0 register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 96. ILA_MON_3_2 register (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 97. ILA_BUF_ERR register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 98. CA_MON register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 99. DEC_FLAGS register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 100.KOUT_FLAG register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 101.K28_LN0_FLAG register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 102.K28_LN1_FLAG register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 103.K28_LN2_FLAG register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 104.K28_LN3_FLAG register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 105.LOCK_CNT_MON_LN01 register (address 0Ah) bit description . . . . . . . . . . . . . 65 Table 106.ILA_MON_3_2 register (address 0Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 107.LOCK_CNT_MON_LN23 register (address 0Ch) bit description . . . . . . . . . . . . . 65 Table 108.FLAG_CNT_LSB_LN0 register (address 10h) bit description . . . . . . . . . . . . . . 65 Table 109.FLAG_CNT_MSB_LN0 register (address 11h) bit description . . . . . . . . . . . . . . 65 Table 110.FLAG_CNT_LSB_LN1 register
bit description . . . . . . . . . . . . . . . . . . . . . . . . .47 Table 59. MISC_CNTRLS register (address 1Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . .47 Table 60. IO_MUX_CNTRL0 register (address 1Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .48 Table 61. IO_MUX_CNTRL1 register (address 1Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .48 Table 62. DIG_VERSION register (address 1Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .49 Table 63. JRX_ANA_VERSION register (address 1Eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .49 Table 64. PAGE_ADDRESS register (address 1Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .49 Table 65. Page 4 register allocation map . . . . . . . . . . . .50 Table 66. SR_DLP_0 register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .52 Table 67. SR_DLP_1 register (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .52 Table 68. FORCE_LOCK register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .52 Table 69. MAN_LOCK_LN_1_0 register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 Table 70. MAN_LOCK_2_0 register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 Table 71. CA_CNTRL register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 Table 72. SCR-CNTRL register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .54 Table 73. ILA_CNTRL register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .55 Table 74. FORCE_ALIGN register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .55 Table 75. MAN_ALIGN_LN_0_1 register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .55 Table 76. MAN_ALIGN_LN_0_1 register (address 0Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . .55 Table 77. FA_ERR_HANDLING register (address 0Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .56 Table 78. SYNCOUT_MODE register (address 0Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .57 Table 79. LANE_POLARITY register (address 1Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .57 Table 80. LANE_SELECT register (address 0Eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .58 Table 81. SOFT_RESET_SCRAMBLER register (address 10h) bit description . . . . . . . . . . . . . .58 Table 82. INIT_SCR_S15T8_LN0 register (address 11h) bit description . . . . . . . . . . . . . .58 Table 83. INIT_SCR_S7T1_LN0 (address 12h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .59 Table 84. INIT_SCR_S15T8_LN1 register
continued >>
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
84 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 137.LN0_CFG_13 register (address 0Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 138.LN1_CFG_0 register (address 10h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 139.LN1_CFG_1 register (address 11h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 140.LN1_CFG_2 register (address 12h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 141.LN1_CFG_3 register (address 13h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 142.LN1_CFG_4 register (address 14h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 143.LN1_CFG_5 register (address 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 144.LN1_CFG_6 register (address 16h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 145.LN1_CFG_7 register (address 17h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 146.LN1_CFG_8 register (address 18h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 147.LN1_CFG_9 register (address 19h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 148.LN1_CFG_10 register (address 1Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 149.LN1_CFG_11 register (address 1Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 150.LN1_CFG_12 register (address 1Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 151.LN1_CFG_13 register (address 1Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 152.PAGE_ADDRESS register (address 1Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 153.Page 7 register allocation map . . . . . . . . . . . . 74 Table 154.LN2_CFG_0 register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 155.LN2_CFG_1 register (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 156.LN2_CFG_2 register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 157.LN2_CFG_3 register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 158.LN2_CFG_4 register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 159.LN2_CFG_5 register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 160.LN2_CFG_6 register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 161.LN2_CFG_7 register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 162.LN2_CFG_8 register (address 08h)
(address 12h) bit description . . . . . . . . . . . . . .65 Table 111.FLAG_CNT_MSB_LN1 register (address 13h) bit description . . . . . . . . . . . . . .65 Table 112.FLAG_CNT_LSB_LN2 register (address 14h) bit description . . . . . . . . . . . . . .66 Table 113.FLAG_CNT_MSB_LN2 register (address 15h) bit description . . . . . . . . . . . . . .66 Table 114.FLAG_CNT_LSB_LN3 register (address 16h) bit description . . . . . . . . . . . . . .66 Table 115.FLAG_CNT_MSB_LN3 register (address 17h) bit description . . . . . . . . . . . . . .66 Table 116.BER_LEVEL register (address 19h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .66 Table 117.INTR_ENA register (address 1Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . .66 Table 118.CNTRL_FLAGCNT_LN01 register (address 1Bh) bit description . . . . . . . . . . . . . .67 Table 119.CNTRL_FLAGCNT_LN23 register (address 1Ch) bit description . . . . . . . . . . . . . .67 Table 120.MON_FLAGS_RESET register (address 1Dh) bit description . . . . . . . . . . . . . .67 Table 121.DBG_CNTRL register (address 1Eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .68 Table 122.PAGE_ADDRESS register (address 1Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .68 Table 123.Page 6 register allocation map . . . . . . . . . . . .69 Table 124.LN0_CFG_0 register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 125.LN0_CFG_1 register (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 126.LN0_CFG_2 register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 127.LN0_CFG_3 register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 128.LN0_CFG_4 register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 129.LN0_CFG_5 register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 130.LN0_CFG_6 register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 131.LN0_CFG_7 register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 132.LN0_CFG_8 register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .71 Table 133.LN0_CFG_9 register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .72 Table 134.LN0_CFG_10 register (address 0Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . .72 Table 135.LN0_CFG_11 register (address 0Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .72 Table 136.LN0_CFG_12 register (address 0Ch)
continued >>
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
85 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
bit description . . . . . . . . . . . . . . . . . . . . . . . . .76 Table 163.LN2_CFG_9 register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .77 Table 164.LN2_CFG_10 register (address 0Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . .77 Table 165.LN2_CFG_11 register (address 0Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .77 Table 166.LN2_CFG_12 register (address 0Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .77 Table 167.LN2_CFG_13 register (address 0Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .77 Table 168.LN3_CFG_0 register (address 10h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .77 Table 169.LN3_CFG_1 register (address 11h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .77 Table 170.LN3_CFG_2 register (address 12h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .77 Table 171.LN3_CFG_3 register (address 13h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .77 Table 172.LN3_CFG_4 register (address 14h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .77 Table 173.LN3_CFG_5 register (address 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .77 Table 174.LN3_CFG_6 register (address 16h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .78 Table 175.LN3_CFG_7 register (address 17h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .78 Table 176.LN3_CFG_8 register (address 18h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .78 Table 177.LN3_CFG_9 register (address 19h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .78 Table 178.LN3_CFG_10 register (address 1Ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . .78 Table 179.LN3_CFG_11 register (address 1Bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .78 Table 180.LN3_CFG_12 register (address 1Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .78 Table 181.LN3_CFG_13 register (address 1Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .78 Table 182.PAGE_ADDRESS register (address 1Fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .78 Table 183.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .80 Table 184.Revision history . . . . . . . . . . . . . . . . . . . . . . . .81
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
86 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
17. Figures
Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .4 JESD204A receiver . . . . . . . . . . . . . . . . . . . . . . .15 Lane input termination . . . . . . . . . . . . . . . . . . . . .16 DC coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 AC coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 SYNC_OUT timing. . . . . . . . . . . . . . . . . . . . . . . .17 Frame assembly. . . . . . . . . . . . . . . . . . . . . . . . . .20 SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 SPI timing diagram. . . . . . . . . . . . . . . . . . . . . . . .22 LVDS clock configuration . . . . . . . . . . . . . . . . . . .23 Interfacing CML to LVDS . . . . . . . . . . . . . . . . . . .23 Internal reference configuration . . . . . . . . . . . . . .27 Equivalent analog output circuit (one DAC) . . . . .29 1 Vo(p-p) differential output with transformer . . . . .31 2 Vo(p-p) differential output with transformer . . . . .31 An example of a DC interface to a 1.7 Vi(cm) AQM . . . . . . . . . . . . . . . . . . . . . . . . .32 An example of a DC interface to a 3.3 Vi(cm) AQM . . . . . . . . . . . . . . . . . . . . . . . . .32 An example of a DC interface to a 1.7 Vi(cm) AQM when using auxiliary DACs. . . .33 An example of a DC interface to a 3.3 Vi(cm) AQM when using auxiliary DACs. . . .33 An example of an AC interface to a 0.5 Vi(cm) AQM when using auxiliary DACs. . . .34 Package outline SOT638 (HTQFP100) . . . . . . . .79
DAC1408D650_1
(c) NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 01 -- 26 May 2009
87 of 88
NXP Semiconductors
DAC1408D650
Dual 14-bit DAC, up to 650 Msps, 2x and 4x interpolating
18. Contents
General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal characteristics. . . . . . . . . . . . . . . . . . . 8 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Application information. . . . . . . . . . . . . . . . . . 14 General description. . . . . . . . . . . . . . . . . . . . . 14 JESD204A receiver . . . . . . . . . . . . . . . . . . . . 15 Lane input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Sync & word align . . . . . . . . . . . . . . . . . . . . . . 16 K detect & word align . . . . . . . . . . . . . . . . . . . 17 Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Inter lane alignment . . . . . . . . . . . . . . . . . . . . 18 Frame assembly . . . . . . . . . . . . . . . . . . . . . . . 19 Serial interface (SPI). . . . . . . . . . . . . . . . . . . . 20 Protocol description . . . . . . . . . . . . . . . . . . . . 20 SPI timing description . . . . . . . . . . . . . . . . . . . 21 Clock inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 23 FIR Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Quadrature modulator and Numerically Controlled Oscillator (NCO) . . . . . . . . . . . . . . 25 10.6.1 NCO in 32-bit . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.6.2 Low-power NCO . . . . . . . . . . . . . . . . . . . . . . . 25 10.6.3 Minus 3dB. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.7 x / (sin x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 10.8 DAC transfer function . . . . . . . . . . . . . . . . . . . 26 10.9 Full-scale current . . . . . . . . . . . . . . . . . . . . . . 27 10.9.1 Regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.9.1.1 External regulation . . . . . . . . . . . . . . . . . . . . . 27 10.9.2 Full-scale current adjustment . . . . . . . . . . . . . 27 10.10 Digital offset adjustment . . . . . . . . . . . . . . . . . 28 10.11 Analog output . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.12 Auxiliary DACs . . . . . . . . . . . . . . . . . . . . . . . . 30 10.13 Output configuration . . . . . . . . . . . . . . . . . . . . 31 10.13.1 Basic output configuration . . . . . . . . . . . . . . . 31 10.13.2 DC interface to an Analog Quadrature Modulator (AQM) . . . . . . . . . . . . . . . . . . . . . . 32 10.13.3 AC interface to an Analog Quadrature Modulator (AQM) . . . . . . . . . . . . . . . . . . . . . . 34 10.14 Power and grounding . . . . . . . . . . . . . . . . . . . 34 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 10.2.6 10.3 10.3.1 10.3.2 10.4 10.5 10.6 10.15 Configuration interface . . . . . . . . . . . . . . . . . . 10.15.1 Register description . . . . . . . . . . . . . . . . . . . . 10.15.2 Detailed descriptions of registers . . . . . . . . . . 10.15.2.1 Page 0 allocation map description . . . . . . . . . 10.15.2.2 Page 0 bit definition detailed description . . . . 10.15.2.3 Page 2 allocation map description . . . . . . . . . 10.15.2.4 Page 2 bit definition detailed description . . . . 10.15.2.5 Page 4 allocation map description . . . . . . . . . 10.15.2.6 Page 4 bit definition detailed description . . . . 10.15.2.7 Page 5 allocation map description . . . . . . . . . 10.15.2.8 Page 5 bit definition detailed description . . . . 10.15.2.9 Page 6 allocation map description . . . . . . . . . 10.15.2.10Page 6 bit definition detailed description . . . . 10.15.2.11Page 7 allocation map description . . . . . . . . . 10.15.2.12Page 7 bit definition detailed description . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information . . . . . . . . . . . . . . . . . . . . . . 14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information . . . . . . . . . . . . . . . . . . . . 16 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 35 35 36 37 42 44 50 52 61 63 69 71 74 76 79 80 81 82 82 82 82 82 82 83 87 88
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 26 May 2009 Document identifier: DAC1408D650_1

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